MC68040RC40A Freescale Semiconductor, MC68040RC40A Datasheet - Page 248

• Manufacturer Part Number: MC68040RC40A
• Description: IC MICROPROCESSOR 32BIT 179-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC40A

• Processor Type: M680x0 32-Bit
• Speed: 40MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.2.3 Floating-Point Status Register (FPSR)
The FPSR (see Figure 9-1) contains a floating-point condition code (FPCC) byte, a
quotient byte, a floating-point exception status byte (EXC), and a floating-point accrued
exception byte (AEXC). The user can read or write to all bits in the FPSR. Execution of
most floating-point instructions modifies this register. The reset function or a restore
operation of the null state clears the FPSR. Floating-point conditional operations are not
guaranteed if the FPSR is written directly, because the FPSR is only valid as a result of a
floating-point instruction.
9.2.3.1 FLOATING-POINT CONDITION CODE BYTE. The FPCC byte (see Figure 9-3)
contains four condition code bits that are set at the end of all arithmetic instructions
involving the floating-point data registers. These bits are sign of mantissa (N), zero (Z),
infinity (I), and NAN. The FMOVE FPm,< ea>, FMOVEM FPm, and FMOVE FPCR
instructions do not affect the FPCC.
To aid programmers of floating-point subroutine libraries, the MC68040 implements the
four FPCC bits in hardware instead of only implementing the four IEEE conditions. An
instruction derives the IEEE conditions when needed. For example, the programmers of a
complex arithmetic multiply subroutine usually prefer to handle special data types such as
9-4
BSUN
15
SNAN OPERR
31
14
13
30
EXCEPTION ENABLE
OVFL
0
12
Figure 9-2. Floating-Point Control Register
29
Figure 9-3. FPSR Condition Code Byte
Freescale Semiconductor, Inc.
UNFL
11
For More Information On This Product,
28
10
DZ
M68040 USER’S MANUAL
Go to: www.freescale.com
INEX2 INEX1
27
N
9
8
26
Z
7
PREC
25
I
6
NAN
24
5
RND
MODE CONTROL
NOT-A-NUMBER OR UNORDERED
INFINITY
ZERO
NEGATIVE
4
3
ROUNDING MODE
ROUNDING PRECISION
INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
BRANCH/SET ON UNORDERED
OVERFLOW
OPERAND ERROR
SIGNALING NOT-A-NUMBER
2
0
1
MOTOROLA
0