TS68020VR16 Atmel, TS68020VR16 Datasheet - Page 37

• Manufacturer Part Number: TS68020VR16
• Description: IC MPU 32BIT 16.67MHZ 114PGA
• Manufacturer: Atmel

Specifications of TS68020VR16

• Processor Type: 68000 32-Bit
• Speed: 16.67MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Primitives/Response
Exceptions
Kinds of Exceptions
Exception Processing
Sequence
2115A–HIREL–07/02
When the main processor encounters the next co-processor instruction, the main pro-
cessor queries the co-processor until the co-processor is ready; meanwhile, the main
processor can go on to service interrupts and do a context switch to execute other tasks,
for example.
Each co-processor instruction type has specific requirements based on this simplified
protocol. The co-processor interface may use as many extension words as requires to
implement a co-processor instruction.
The response register is the means by which the co-processor communicates service
requests to the main processor. The content of the co-processor response register is a
primitive instruction to the main processor which is read during co-processor communi-
cation by the main processor. The main processor “executes” this primitive, thereby
providing the services requires by the co-processor. Table 11 summarizes the co-pro-
cessor primitives that the TS68020 accepts.
Exception can be generated by either internal or external causes. The externally gener-
ated exceptions are the interrupts, the bus error, and reset requests. The interrupts are
requests from peripheral devices for processor action while the bus error and reset pins
are used for access control and processor restart. The internally generated exceptions
come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc,
TRAPV, cpTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as
part of their execution. Tracing behaves like a very high priority, internally generated
interrupt whenever it is processed. The other internally generated exceptions are
caused by illegal instructions, instruction fetches from odd addresses, and privilege
violations.
Exception processing occurs in four steps. During the first step, an internal copy is made
of the status register. After the copy is made, the special processor state bits in the sta-
tus register are changed. The S bit is set, putting the processor into supervisor privilege
state. Also, the T1 and T0 bits are negated, allowing the exception handler to execute
unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask
is also updated.
In the second step, the vector number of the exception is determined. For interrupts, the
vector number is obtained by a processor read that is classified as an interrupt acknowl-
edge cycle. For co-processor detected exceptions, the victor number is included in the
co-processor exception primitive response. For all other exceptions, internal logic pro-
vides the vector number. This vector number is then used to generate the address of the
exception vector.
The third step is to save the current processor status. The exception stack frame is cre-
ated and filled on the supervisor stack. In order to minimize the amount of machine state
that is saved, various stack frame sizes are used to contain the processor state depend-
ing on the type of exception and where it occurred during instruction execution. If the
exception is an interrupt and the M bit is on, the M bit is forced off, and a short four word
exception stack frame is saved on the master stack which indicates that the exception is
saved on the interrupt stack. If the exception is a reset, the M bit is simply forced off, and
the reset vector is accessed.
TS68020
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