TSPC603RVA8LC Atmel, TSPC603RVA8LC Datasheet - Page 37

• Manufacturer Part Number: TSPC603RVA8LC
• Description: IC MPU 32BIT 8MHZ 240CERQUAD
• Manufacturer: Atmel

Specifications of TSPC603RVA8LC

• Processor Type: PowerPC 603e 32-Bit RISC
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 240-Cerquad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

12.3.3
12.3.4
5410B–HIREL–09/05
Exception Model
PowerPC Exception Model
The following subsections describe the PowerPC exception model and the 603R
implementation.
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of external singles, errors, or unusual conditions arising in the execution of instructions,
and differ from the arithmetic exceptions defined by the IEEE for floating-point operations. When
exceptions occur, information about the state of the processor is saved to certain registers and
the processor begins execution at an address (exception vector) predetermined for each excep-
tion. Processing of exceptions occurs in supervisor mode.
Although multiple exception conditions can map to a single exception vector, a more specific
condition may be determined by examining a register associated with the exception - for exam-
ple, the DSISR and the FPSCR. Additionally, some exception conditions can be explicitly
enabled or disabled by software.
The PowerPC architecture requires that exceptions be handled in program order; therefore,
although a particular implementation may recognize exception conditions out of order, they are
presented strictly in order. When an instruction-caused exception is recognized, any unexecuted
instructions that appear earlier in the instruction stream, including any that have not yet entered
the execute state, must be completed before the exception is taken. Any exceptions caused by
such instructions are handled first. Likewise, exceptions that are asynchronous and precise are
recognized when they occur, but are not handled until the instruction currently in the completion
state successfully completes execution or generates an exception, and the completed store
queue is emptied.
Unless a catastrophe event causes a system reset or machine check exception, only one excep-
tion is handled at a time. If, for example, a single instruction encounters multiple exception
conditions, those conditions are encountered sequentially.
After the exception handler handles an exception, the instruction execution continues until the
next exception condition is encountered. However, in many cases there is no attempt to re-exe-
cute the instruction. This method of recognizing and handling exception conditions sequentially
guarantees that exceptions are recoverable.
Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the
program state from being lost due to a system reset and machine check exception or to an
instruction-caused exception in the exception handler, and before enabling external interrupts.
The PowerPC architecture supports four types of exceptions:
• Synchronous, Precise – these are caused by instructions. All instruction-caused exceptions
are handled precisely; that is, the machine state at the time the exception occurs is known
and can be completely restored. This means that (excluding the trap and system call
exceptions) the address of the faulting instruction is provided to the exception handler and
that neither the faulting instruction nor subsequent instructions in the code stream will
complete execution before the exception is taken. Once the exception is processed,
execution resumes at the address of the faulting instruction (or at an alternate address
provided by the exception handler). When an exception is taken due to a trap or system call
instruction, execution resumes at an address provided by the handler.
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