668-0011 Rabbit Semiconductor, 668-0011 Datasheet - Page 167
668-0011
Manufacturer Part Number
668-0011
Description
IC MPU RABIT3000A 55.5MHZ128LQFP
Manufacturer
Rabbit Semiconductor
Datasheet
1.20-668-0011.pdf
(312 pages)
Specifications of 668-0011
Rohs Status
RoHS non-compliant
Processor Type
Rabbit 3000 8-Bit
Speed
55.5MHz
Voltage
2.5V, 2.7V, 3V, 3.3V
Mounting Type
Surface Mount
Package / Case
128-LQFP
Features
-
Other names
316-1043
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19.1 Overview
The slave port is a parallel communication port that can be used to communicate with an
external master device. The slave port consists of three data input and data output regis-
ters, and a status register.
The data input registers are written by the master (the external device) and are read by the
processor. The data output registers are written by the processor and are read by the master.
Note that the data registers are named from the point of view of the processor. The slave
device can only read the data input registers and write to the data output registers. Similarly,
the master device can only read the data input registers and write the data output registers.
Both devices can read and write to the status register.
The status register contains the interrupt status bits and a status flag corresponding to each
data input or data output register to indicate the empty or full status of the data register.
Data registers are marked full when written by the source side of the interface, and are
marked empty when read by the destination side of the interface.
The hardware interface to the external master consists of an 8-bit bidirectional data bus
with a read strobe, write strobe, and chip select. There are two address lines that select one
of the three data registers or the status register.
A slave attention signal is asserted when the processor writes to one of the slave port data
registers (SPD0R), and can be deasserted by the master by performing a dummy write to
the status register. This signal can be used to interrupt the master to indicate that the mas-
ter needs to read data from the slave.
The slave port interrupt is asserted when the master writes to SPD0R. The processor clears
this interrupt condition by writing to the status register.
Chapter 19 Slave Port
Slave Port Address
Table 19-1. Slave Port Addresses
00
01
10
11
Slave Port Register
Data Register 0
Data Register 1
Data Register 2
Status Register
19. S
LAVE
P
ORT
157
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