FWIXP420BB Intel, FWIXP420BB Datasheet - Page 28

• Manufacturer Part Number: FWIXP420BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of FWIXP420BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 266MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 852278

2.2.2
Intel
Datasheet
28
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
The memory pipe has eight stages:
The MAC pipe has six to nine stages:
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3,
and/or MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to
successfully predict the outcome of branch instructions. The branch target buffer
provides such a means.
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the
target address associated with the branch instruction, and a previous history of the
branch being taken or not taken. The history is recorded as one of four states:
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or
weakly taken, the instruction at the branch target address is fetched. When its history
is strongly or weakly not-taken, the next sequential instruction is fetched. In either
case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is
taken. This data enters the BTB in a slot with a history of strongly not-taken
(overwriting previous data when present).
• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
• Integer Writeback
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback
• Strongly
. . . then finish with the following memory stages:
. . . then finish with the following MAC stages:
taken
• Weakly taken
Intel
®
IXP42X product line and IXC1100 control plane processors
• Weakly not
taken
Document Number: 252479-006US
• Strongly not taken
August 2006