PRIXP420BB Intel, PRIXP420BB Datasheet - Page 20

• Manufacturer Part Number: PRIXP420BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP420BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866260

Non-Core Errata
Workaround:
Status:
11.
Problem:
Implication:
Workaround:
20
Here are two possible software timer work arounds:
No
Character Time-Out Interrupt Sticks Under Certain Software Timing
Conditions (SCR 2235)
Character time-out interrupt doesn’t clear and the DR bit is not set.
The processor can get into a continuous interrupt loop where the character time-out interrupt is
SET although there is no data in the FIFO.
This errata results from the following implementation:
If the Step
If this situation has been assessed correctly, the workaround’s disabling of the interrupt — via
IER[4] (step 2.) — will prevent the RTO interrupt SM from being entered a second time. It is safe
to re-enable the interrupt after the FIFO is empty, as the FIFO empty condition also prevents the
RTO interrupt SM from being entered. To execute:
1. Read Line Status Register (LSR) and check for errors.
2. Read Data from FIFO.
3. Software Delay.
4. Read LSR, check for errors, and LOOP back to Step
5. DONE.
•
•
Fix.
Only enable one of the following timers: GP0, GP1, Timestamp, or Watchdog interrupt. If the
watchdog timer is configured to do a soft reset, the GP0,GP1, or the Timestamp can be used in
addition to the watchdog timer.
Note there is a counter in the IXP42X product line PMU that can be used.
If the first work around is insufficient, an improved timer interrupt handler would be needed.
Pseudo-code for such an improved timer handler follows:
Intel
10. Load R9 [GP timer 1 register].
12. If (R8 > R5), then GP timer 0 expired: Software needs to acknowledge.
13. If (R9 > R6), then GP timer 1 expired: Software needs to acknowledge.
11. If (R7 < R4), then timestamp expired: Software needs to acknowledge.
1. Interrupt handler determines there is a timer interrupt.
2. Load R0 [timer status register].
3. Load R4 [timestamp register].
4. Load R5 [GP timer 0 register].
5. Load R6 [GP timer 1 register].
6. Software acknowledges timers that have expired.
7. Store R0 [timer status register] at software clears timer status.
8. Load R7 [timestamp register].
9. Load R8 [GP timer 0 register].
®
3.
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
is placed in front of 1., the issue never occurs.
2.
— if DR bit in LSR is SET.