PRIXP420BB Intel, PRIXP420BB Datasheet - Page 26

• Manufacturer Part Number: PRIXP420BB
• Description: IC NETWRK PROCESSR 266MHZ 492BGA
• Manufacturer: Intel

Specifications of PRIXP420BB

• Processor Type: Network
• Features: XScale Core
• Speed: 266MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 492-BGA
• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 866260

Non-Core Errata
Workaround:
Status:
23.
Problem:
Implication:
Workaround:
Status:
24.
Problem:
Implication:
Workaround:
Status:
25.
Problem:
Implication:
Workaround:
Status:
26
None.
No
Ethernet Coprocessors - Length Errors on Received Frames (SCR 711)
The IXP42X product line and IXC1100 control plane processors have an Ethernet Coprocessor that
is configured by Intel XScale core software. [Note that some IXP42X product line and IXC1100
control plane processors have two Ethernet Coprocessors.] The Ethernet Coprocessor can indicate
length error on received frames only when stripping of pad bytes from the received frame is
enabled.
Length Errors on received frames when pad stripping is disabled will not be indicated to the NPE
software when it reads the Receive status. When pad stripping is enabled, length error indicates
that the packet length is not equal to 64 bytes, and the entry in the length field is less than 46, but
not zero.
None.
No
PCI DC Parameter VIH Marginality Issue (SCR 3121)
The input-high voltage (VIH) for the PCI bus signals does not meet the documented specification.
In the Intel
Datasheet (252479), Table 25 (“PCI DC Parameters”) specifies the VIH minimum value as 0.5
VCCP. This specification is changed to 0.6 VCCP.
At 66-MHz PCI bus operation, the Tprop timing would be a slightly longer. Refer to the PCI Local
Bus Specification, Revision 2.2, and see the section “System Timing Budget.”
To ensure proper PCI bus operation at 66 MHz, designers must pay careful attention to the
maximum trace length and loading. Board simulation should be done prior to finalizing layout. For
PCI topologies and routing recommendations, see the Intel
Control Plane Network Processors Hardware Design Guidelines (252817).
No
False PCI DMA Completion Notification Causing Data Corruption
(SCR 3910)
The PADC1, PADC0, APDC1, and APDC0 complete bits in the PCI_DMACTRL register will not
be cleared under certain conditions when the Intel XScale core processor performs a write 1 to
clear to the appropriate bit. If another PCI DMA transfer is initiated after the clear to the
PCI_DMACTRL register, an indication of complete will occur before the DMA transfer has been
finished (because the complete bit may have not been cleared).
DMA data will not be transferred as programmed in the PCI DMA registers.
There are two workarounds available:
No
1. Mask the PADC/APDC enables in the PCI_INTEN register and use software to poll the EN
2. If interrupts are preferred, after writing a 1 to clear the appropriate complete bit in the
Fix.
Fix.
Fix.
Fix.
(bit 31) of the appropriate PCI_ATPDMA0_LENGTH, PCI_PTADMA0_LENGTH and
PCI_ATPDMA1_LENGTH, PCI_PTADMA1_LENGTH register to indicate whether the
DMA transfer was completed.
PCI_DMACTRL register, read the PCI_DMACTRL register back and ensure the appropriate
complete bit was cleared. If not cleared, repeat this step until the appropriate complete bit is
cleared.
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP4XX Product Line and IXC1100