MMA8110EG Freescale Semiconductor, MMA8110EG Datasheet - Page 2
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MMA8110EG
Manufacturer Part Number
MMA8110EG
Description
Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
Manufacturer
Freescale Semiconductor
Series
MMA81r
Datasheet
1.MMA8110EG.pdf
(47 pages)
Specifications of MMA8110EG
Sensing Axis
Z
Acceleration
100 g
Sensitivity
4.01 mV/g
Package / Case
SOIC-20 Wide
Axis
Z
Acceleration Range
±100g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
SECTION 1 GENERAL DESCRIPTION
MMA81XXEG/MMA82XXEG/MMA82XXTEG family is a satellite accelerometer which is comprised of a single axis, variable ca-
pacitance sensing element with a single channel interface IC. The interface IC converts the analog signal to a digital format which
is transmitted in accordance with the DSI-2.0 specification.
1.1
Signal conditioning begins with a Capacitance to Voltage conversion (C to V) followed by a 2-stage switched capacitor amplifier.
This amplifier has adjustable offset and gain trimming and is followed by a low-pass switched capacitor filter with Bessel function.
Offset and gain of the interface IC are trimmed during the manufacturing process. Following the filter the signal passes to the
output stage. The output stage sensitivity incorporates temperature compensation.
The output of the accelerometer signal conditioning is converted to a digital signal by an A/D converter. After this conversion the
resultant digital word is converted to a serial data stream which may be transmitted via the DSI bus. Power for the device is
derived from voltage applied to the BUSIN/BUSOUT and V
connected to the H
integrated regulator supplies fixed voltage to internal circuitry.
A self-test voltage may be applied to the electrostatic deflection plate in the sensing element. Self-Test voltage is factory trimmed.
Other support circuits include a bandgap voltage reference for the bias sources and the self-test voltage.
A total of 128 bits of One-Time Programmable (OTP) memory, are provided for storage of factory trim data, serial number and
device characteristics. Eighty OTP bits are available for customer programming. These eighty OTP bits may be programmed via
the DSI Bus or through the serial test/trim interface. OTP integrity is verified through continuous parity checking. Separate parity
bits are provided for factory and customer programmed data. In the event that a parity fault is detected, the reserved value of
zero is transmitted in response to a Read Acceleration Data command.
A block diagram illustrating the major elements of the device is shown in
MMA81XXEG
2
MMA8225EGR2
MMA8225EG
MMA8215EGR2
MMA8215EG
MMA8210TEGR2
MMA8210TEG
MMA8205TEGR2
MMA8205TEG
MMA8204EGR2
MMA8204EG
MMA8202EGR2
MMA8202EG
MMA8125EGR2
MMA8125EG
MMA8115EGR2
MMA8115EG
MMA8110EGR2
MMA8110EG
MMA8104EGR2
MMA8104EG
Device Name
OVERVIEW
CAP
pin. During data transmissions, the device operates from stored charge on the external capacitor. An
X-axis g-Level
250
250
150
150
100
100
50
50
40
40
20
20
—
—
—
—
—
—
—
—
Z-axis g-Level
250
250
150
150
100
100
ORDERING INFORMATION
40
40
—
—
—
—
—
—
—
—
—
—
—
—
SS
Temperature Range
pins. Bus voltage is rectified and applied to an external capacitor
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
-40 to +125°C
Figure
1-1.
SOIC 16 Package
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475-01
475-01
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