MMA8110EGR2 Freescale Semiconductor, MMA8110EGR2 Datasheet - Page 13
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MMA8110EGR2
Manufacturer Part Number
MMA8110EGR2
Description
Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
Manufacturer
Freescale Semiconductor
Series
MMA81r
Datasheet
1.MMA8110EG.pdf
(47 pages)
Specifications of MMA8110EGR2
Sensing Axis
Z
Acceleration
100 g
Sensitivity
4.01 mV/g
Package / Case
SOIC-20 Wide
Axis
Z
Acceleration Range
±100g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Sensors
Freescale Semiconductor
3.2.6.4
This bit may be programmed at any time, regardless of the state of LOCK2. This bit is intended to be programmed when a module
has been determined by the DSI Bus Master to be defective. Programming this bit after LOCK2 has been set will cause the device
to respond to short word Read Acceleration Data commands with a zero response. Acceleration results are not affected by this
bit when long word Read Acceleration Data commands are executed, however the Status (S) bit will be set in the response.
1 - Device responds to Read Acceleration Data command with zero value
0 - Device responds normally to Read Acceleration Data command
3.2.6.5
These bits define the pre-programmed DSI Bus device address.
3.3
Two different methods of programming the eighty customer defined bits are supported. In test mode, these may be programmed
in the same manner as factory programmed OTP bits. Additionally, the Read Write NVM DSI bus command may be used. Test
mode programming operations are described in
Section
4.6.3.
OTP PROGRAMMING
Device Disable Bit (DDIS)
Device Address (AD3 - AD0)
Appendix
A.3. Read Write NVM command operation is described in
MMA81XXEG
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