MMA8125EG Freescale Semiconductor, MMA8125EG Datasheet - Page 40
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MMA8125EG
Manufacturer Part Number
MMA8125EG
Description
Board Mount Accelerometers SOURCE ONLY
Manufacturer
Freescale Semiconductor
Series
MMA81r
Datasheet
1.MMA8110EG.pdf
(47 pages)
Specifications of MMA8125EG
Sensing Axis
Z
Acceleration
250 g
Sensitivity
1.6 mV/g
Package / Case
SOIC-16 Wide
Axis
Z
Acceleration Range
±250g
Voltage - Supply
6.3 V ~ 30 V
Output Type
Digital
Bandwidth
-
Interface
SPI
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Test mode is entered when certain conditions are satisfied after power is applied to the device. Communication with the device
is conducted using the SPI when in test mode. Two test mode operations are of interest to the customer. These operations are
described below. Test mode communication is conducted using the serial peripheral interface (SPI).
A.1
A 16-bit SPI is available for data transfer when the voltage at V
sequence of data values shown above are transferred following reset. See
The state of D
CPHA = 0, CPOL = 0 operation for conventional SPI devices.
A.2
A special device configuration useful for evaluating the performance of the analog-to-digital convertor block is available. When
selected, internal buffers which drive the C
pin, as illustrated in
Appendix A.4
Remove power or lower the voltage at V
MMA81XXEG
40
1.
2.
3.
4.
5.
SPI DATA TRANSFER
ADC TEST MODE
Apply V
Apply V
Transfer the data value $AA to device register address $30 via the SPI.
Transfer the data value $55 to device register address $30 via the SPI.
Transfer the data value $1D to device register address $30 via the SPI.
for details regarding register read and write operations.
IN
is latched on the rising edge of CLK. D
HCAP
TEST
Figure A-1.
to the V
to the H
PP
CAP
APPENDIX A TEST MODE OPERATION
The following sequence of operations must be performed to enter ADC Test Mode. Refer to
/TEST pin.
pin. This may be accomplished through BUSIN if desired.
PP
FIL
/TEST to exit ADC Test Mode.
pin and ADC input are disabled, and the input of the ADC is connected to the C
OUT
changes on the falling edge of CLK. The interface conforms to
PP
/TEST is raised above V
Figure A-4
for details of 16-bit SPI packet.
TEST
. Test mode is entered when the
Freescale Semiconductor
Sensors
FIL