CS42448-CQZ Cirrus Logic Inc, CS42448-CQZ Datasheet - Page 26

• Manufacturer Part Number: CS42448-CQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-CQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 6 ADC/8 DAC
• Thd Plus Noise: - 98 dB ADC / - 98 dB DAC, - 95 dB ADC / - 95 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1033

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4.2.3
4.3
4.3.1
Analog Outputs
Single-Ended Mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the
AINx_MUX bits. See register
lections. Refer to
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion re-
sult. This feature makes it possible to perform a system DC offset calibration by:
1. Running the CS42448 with the high-pass filter enabled until the filter settles. See the Digital Filter
2. Disabling the high-pass filter and freezing the stored DC offset.
The high-pass filter for ADC1/ADC2 can be enabled and disabled.
be independently enabled and disabled.
bit in the register
Initialization
The initialization and Power-Down sequence flow chart is shown in
enters a power-down state upon initial power-up. The interpolation and decimation filters, delta-sigma
modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog
and analog-to-digital converters and switched-capacitor low-pass filters are powered down.
The device remains in the power-down state until the RST pin is brought high. The control port is acces-
sible once RST is high, and the desired register settings can be loaded per the interface descriptions in
the
Once MCLK is valid, VQ will ramp up to VA/2, and the internal voltage references, FILT+_ADC and
FILT+_DAC, will begin powering up to normal operation. Power is applied to the D/A converters and
switched-capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is
valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ra-
tio. After an approximate 2000 sample period delay, normal operation begins.
“Control Port Description and Timing” on page
Characteristics for filter settling time.
“ADC Control & DAC De-Emphasis (Address 05h)” on page
Figure 13 on page 29
“ADC Control & DAC De-Emphasis (Address 05h)” on page 45
for the internal ADC3 analog input topology.
The high-pass filters are controlled using the HPF_FREEZE
35.
The high pass filter for ADC3 can
Figure 12 on page
45.
27. The CS42448
CS42448
for all bit se-
DS648F3