CS42528-CQZ Cirrus Logic Inc, CS42528-CQZ Datasheet - Page 47
![IC CODEC S/PDIF RCVR 64LQFP](/photos/6/80/68064/cs42528-cqz_sml.jpg)
CS42528-CQZ
Manufacturer Part Number
CS42528-CQZ
Description
IC CODEC S/PDIF RCVR 64LQFP
Manufacturer
Cirrus Logic Inc
Type
General Purposer
Datasheet
1.CS42528-CQZ.pdf
(91 pages)
Specifications of CS42528-CQZ
Package / Case
64-LQFP
Data Interface
Serial
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 8
Sigma Delta
Yes
Dynamic Range, Adcs / Dacs (db) Typ
114 / 114
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.13 V ~ 5.25 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Number Of Adc Inputs
2
Number Of Dac Outputs
8
Conversion Rate
192 KSPS
Interface Type
Serial (SPI)
Resolution
24 bit
Operating Supply Voltage
3.3 V, 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 10 C
Number Of Channels
2 ADC/8 DAC
Thd Plus Noise
- 100 dB ADC / - 100 dB DAC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1503 - BOARD EVAL FOR CS42528/CS49300
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1038
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Part Number
Manufacturer
Quantity
Price
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CS42528-CQZ
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Cirrus Logic Inc
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DS586F1
6.3
6.3.1
6.3.2
6.3.3
6.3.4
PDN_RCVR1 PDN_RCVR0
7
Power Control (address 02h)
POWER DOWN RECEIVER (PDN_RCVRX)
POWER DOWN ADC (PDN_ADC)
POWER DOWN DAC PAIRS (PDN_DACX)
POWER DOWN (PDN)
Default = 10
00 - Receiver and PLL in normal operational mode.
01 - Receiver and PLL held in a reset state. Equivalent to setting 11.
10 - Reserved.
11 - Receiver and PLL held in a reset state. Equivalent to setting 01.
Function:
Default = 0
Function:
Default = 0
Function:
Default = 1
Function:
Places the S/PDIF receiver and PLL in a reset state. It is advised that any change of these bits be
made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility
of audible artifacts.
It should be noted that, for Revision C compatibility, PDN_RCVR1 may be set to ‘0’ and receiver op-
eration may be controlled with the PDN_RCVR0 bit.
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to elim-
inate the possibility of audible artifacts.
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
6
PDN_ADC
5
PDN_DAC4
4
PDN_DAC3
3
PDN_DAC2
2
PDN_DAC1
1
CS42528
PDN
0
47