CS42448-DQZ Cirrus Logic Inc, CS42448-DQZ Datasheet - Page 45

• Manufacturer Part Number: CS42448-DQZ
• Description: IC CODEC 108DB 192KHZ 64LQFP
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS42448-DQZ

• Package / Case: 64-LQFP
• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 6 / 8
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 108 (Differential), 102 / 105 (Single-Ended)
• Voltage - Supply, Analog: 3.14 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 5.25 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 10
• Number Of Dac Outputs: 8
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2C, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 6 ADC, 8 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1151 - BOARD EVAL FOR CS42448 CODEC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1615

DS648F3
6.5.4
6.6
6.6.1
ADC1-2_HPF
FREEZE
7
ADC Control & DAC De-Emphasis (Address 05h)
ADC Digital Interface Format (ADC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the ADC serial port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in the section
Interface Channel Allocations,” on page
Note:
ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset
value will be frozen and continue to be subtracted from the conversion result. See
Characteristics” on page
DAC_DIF2
ADC_DIF2 ADC_DIF1 ADC_DIF0
0
1
1
1
1
0
0
0
0
1
1
1
1
ADC3_HPF
FREEZE
The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.
6
DAC_DIF1
1
0
0
1
1
0
0
1
1
0
0
1
1
DAC_DEM
5
13.
“CODEC Digital Interface Formats” on page
DAC_DIF0
Table 12. DAC Digital Interface Formats
Table 13. ADC Digital Interface Formats
0
1
0
1
0
1
0
1
1
0
1
0
1
SINGLE
ADC1
4
34.
Left Justified, up to 24-bit data
I²S, up to 24-bit data
Right Justified, 24-bit data
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
SINGLE
ADC2
Description
Description
3
SINGLE
ADC3
2
31. Refer to
AIN5_MUX
Format
Format
1
Table 9, “Serial Audio
0
1
2
3
4
5
6
3
4
5
6
-
-
“ADC Digital Filter
CS42448
AIN6_MUX
Figure 16
Figure 15
Figure 17
Figure 17
Figure 18
Figure 19
Figure 20
Figure 17
Figure 18
Figure 19
Figure 20
Figure
Figure
0
-
-
45