IDTSTAC9753XXTAEB2XR IDT, Integrated Device Technology Inc, IDTSTAC9753XXTAEB2XR Datasheet - Page 63

• Manufacturer Part Number: IDTSTAC9753XXTAEB2XR
• Description: IC CODEC AC'97 MIC/JACK 48-QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753XXTAEB2XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753XXTAEB2XR

IDT™
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.1.21.
8.1.22.
8.1.23.
CODEC
SR15
SR15
SR7
SR7
D15
D15
D7
D7
00
01
10
11
ID
PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs are controlled by a value in these read/write regis-
ters (that contain a 16-bit unsigned value between 0 and 65535) representing the conversion rate in
Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,
that value will be echoed back when read; otherwise the closest (higher in the case of a tie) sample
rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are
supported for record and playback.
Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) will be loaded with BB80h (48 KHz).
If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48 KHz.
PCM DAC Rate (2Ch)
Default: BB80h (see table20: page63)
PCM LR ADC Rate (32h)
Default: BB80h (see table20: page63)
2-ch Primary w/SPDIF
2-ch Dock CODEC w/SPDIF
+2-ch Surr w/ SPDIF
+2-ch Cntr/LFE w/ SPDIF
SR14
SR14
D14
SR6
D14
SR6
D6
D6
Function
11.025 KHz
Sample Rate
22.05 KHz
44.1 KHz
16 KHz
32 KHz
48 KHz
Note: * indicates the default slot assignment
8 KHz
SR13
SR13
SR5
SR5
D13
D13
D5
D5
Table 20. Hardware Supported Sample Rates
slot assignment
Table 19. AMAP compliant
SPSA = 00
SR12
SR12
3 & 4
3 & 4
3 & 4
3 & 4
SR4
SR4
D12
D12
63
D4
D4
slot assignment
SR11
SR11
SR3
SR3
D11
D11
D3
D3
SPSA = 01
7 & 8*
7 & 8
7 & 8
7 & 8
STAC9752/9753
SR10
SR10
D10
SR2
D10
SR2
D2
D2
slot assignment
SR[15:0] Value
SPSA = 10
AC44h
2B11h
3E80h
7D00h
BB80h
1F40h
5622h
6 & 9*
6 & 9*
6 & 9
6 & 9
SR9
SR1
SR9
SR1
D9
D1
D9
D1
slot assignment
SPSA = 11
10 & 11*
10 & 11
10 & 11
10 & 11
REV 3.3 1206
SR8
SR0
SR8
SR0
D8
D0
D8
D0