IDTSTAC9271D5TAEB4X IDT, Integrated Device Technology Inc, IDTSTAC9271D5TAEB4X Datasheet - Page 29

• Manufacturer Part Number: IDTSTAC9271D5TAEB4X
• Description: IC AUDIO CODEC 10CH HD 5V 48TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec, HDr

Specifications of IDTSTAC9271D5TAEB4X

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 3 / 5
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 105
• Dynamic Range, Adcs / Dacs (db) Typ: 90 / 95
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 3.8 V ~ 4.2 V; 4.28 V ~ 4.73 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9271D5TAEB4X

IDT™
STAC9271/9274
10-CHANNEL HIGH DEFINITION AUDIO CODEC
10-CHANNEL HIGH DEFINITION AUDIO CODEC
Power State
Digital Mics
D0-D3
D0
D1
D2
D3
0
1
2
3
4
DMIC Widget
Single Edge on
DMIC_0 and 1
pin and Single
Date Sample
second DMIC
Enabled?
on one DMIC
Double Edge
DMIC_0 or 1
Double Edge
Double Edge
Single Edge
Edge on the
on either
Table 4. DMIC_CLK and DMIC_0,1 Operation During Power States
Yes
Yes
Yes
Yes
No
N/A
pin.
OR
Table 3. Valid Digital Microphone Configurations
Clock Disabled Input Disabled DMIC_CLK Remains Low
Clock Disabled Input Disabled DMIC_CLK Remains Low
Clock Disabled Input Disabled DMIC_CLK is HIGH-Z with Weak Pull-down
Clock Capable Input Capable
Clock Capable Input Capable
DMIC_CLK
IDT CONFIDENTIAL
ADC Conn.
Output
0, 1, or 2
0, 1, or 2
0, 1, or 2
0, 1, or 2
N/A
29
Available on either DMIC_0 or DMIC_1
Both ADC Channels produce data, may be in phase or out by
1/2 DMIC_CLK period depending upon external configuration
and timing
Available on either DMIC_0 or DMIC_1, External logic
required to support sampling on a single Digital Mic pin
channel on rising edge and second Digital Mic right channel
on falling edge of DMIC_CLK for those digital microphones
that don’t support alternative clock edge capability. If both
DMIC_0 and DMIC_1 are used to support 2 digital
microphones, 2 separate ADC units will be used, however,
this configuration is not recommended since it consumes two
stereo ADC resources.
Requires both DMIC_0 or DMIC_1, External logic required to
support sampling on a single Digital Mic pin channel on rising
edge and second Digital Mic right channel on falling edge of
DMIC_CLK for those digital microphones that don’t support
alternative clock edge capability. Two ADC units are required
to support this configuration
Connected to DMIC_0 and DMIC_1, External logic required
to support sampling on a single Digital Mic pin channel on
rising edge and second Digital Mic right channel on falling
edge of DMIC_CLK for those digital microphones that don’t
support alternative clock edge capability. Two ADC units are
required to support this configuration
DMIC_0,1
DMIC_CLK Output is Enabled when either
DMIC_0 or DMIC_1 Input Widget is Enabled.
Otherwise, the DMIC_CLK remains Low
DMIC_CLK Output is Enabled when either
DMIC_0 or DMIC_1 Input Widget is Enabled.
Otherwise, the DMIC_CLK remains Low
No Digital Microphones
STAC9271/9274
Notes
Notes
PC AUDIO
V 1.1 01/08