IDT821054APF IDT, Integrated Device Technology Inc, IDT821054APF Datasheet - Page 14

• Manufacturer Part Number: IDT821054APF
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054APF

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
A=β ( 0<β<1), the amplitude will be 1.57 ∗ β (V).
tolerances are as the following:
corresponding hexadecimal values before being written to the Coe-
RAM. Refer to
address of the tone coefficients.
generators. When only one tone generator is enabled, or dual tone
generators produce the same tone signal and frequency of the tone
meets the ring signal requirement (10 Hz to 100 Hz), a ring signal will be
generated and output to the VOUT pin.
2.9
channels. The level meter is designed to emulate the off-chip PCM test
equipment so as to facilitate the line-card, subscriber line and users
telephone set monitoring. The level meter tests the return signal and
reports the measurement result via the MPI interface. When combined
with tone generation and loopbacks, it allows the microprocessor to test
the channel integrity. The signal on the channel selected by the CS[1:0]
bits in GREG21 will be metered.
level meter counter register (GREG20) is used to set the value of time
cycles for sampling the PCM data (8 kHz sampling rate). The output of
level meter is sent to the level meter result registers GREG18 and
GREG19. The LVLL[7:0] bits in GREG18 contain the lower 7 bits of the
result and a data-ready bit (LVLL[0]), while the LVLH[7:0] bits in
GREG19 contain the higher 8 bits of the result. An internal accumulator
sums the rectified samples until the value set in GREG20 is reached. By
then, the LVLL[0] bit is set to ‘1’ and accumulation result is latched into
GREG18 and GREG19 simultaneously.
GREG18 will be reset. It will be set to ‘1’ again by a new data available.
The contents of GREG18 and GREG19 will be overwritten by the
following metering result if they have not been read out yet. To read the
level meter result registers, it is recommended to read GREG18 (lower
byte of result) first.
A = 0, corresponds to the minimum amplitude of 0 V.
It is a linear relationship between 'A' and the amplitude. That is, if
The frequency range is from 25 Hz to 3400 Hz. The frequency
25 Hz < f < 40 Hz, tolerance < ±12%
40 Hz < f < 60 Hz, tolerance < ±5%
60 Hz < f < 100 Hz, tolerance < ±2.5%
100 Hz < f < 3400 Hz, tolerance < ±1%
The frequency and amplitude coefficients should be converted to
The ring signal is a special signal generated by the dual tone
The IDT821054A integrates a level meter which is shared by all 4
The level meter is enabled by setting the LMO bit in GREG21 to ‘1’. A
Once the higher byte of result (GREG19) is read, the LVLL[0] bit in
The L/C bit in GREG21 determines the level meter operation mode. If
LEVEL METERING
“9 Appendix: IDT821054A Coe-RAM Mapping”
for the
14
the L/C bit is ‘1’, it means that metering mode is selected. In this mode,
the linear PCM data will be sent to the level meter and the metering
result will be output to GREG18 and GREG19. With this result, the
signal level can be calculated.
level can be calculated by the following formula:
by the following formula:
mode, the compressed PCM data will be output to GREG19
transparently without metering.
2.10
independently by setting the PD bit in LREG9 to ‘1’. If one channel is
powered down and enters the standby mode, the PCM data transfer and
the D/A, A/D converters of this channel will be disabled. In this way, the
power consumption of the device can be reduced.
be powered down. All circuits that contain programmed information
retain their data after power down. The microprocessor interface is
always active so that new commands can be received and executed.
2.11
suspend mode saves much more power consumption than the standby
mode. In this mode, the PLL block is turned off and the DSP operation is
disabled. Only global and local commands can be executed, the RAM
operation is disabled as the internal clock has been turned off. The PLL
block is powered down by setting the PPD bit in GREG22 to ‘1’. Once
the PLL and all four channels are powered down, the IDT821054A will
enter the suspend mode.
For A-law compressed PCM code or linear PCM code, the signal
For
LM
LM
If the L/C bit is ‘0’, it means that message mode is selected. In this
Refer to the Application Note for further details on the level meter.
Each individual channel of the IDT821054A can be powered down
When the IDT821054A is powered up or reset, all four channels will
A suspend mode is provided for the whole chip to save power. The
A dbm0
A dbm0
(
(
Result
Countnumber
µ
-law compressed PCM code, the signal level can be calculated
CHANNEL POWER DOWN/STANDBY MODE
POWER DOWN/SUSPEND MODE
:
)
)
=
=
:the count number of the level meter (set in GREG20).
20
20
the value in the level meter result registers (GREG18
& GREG19);
×
×
log
log






------------------------------------------------------------- -
LM
------------------------------------------------------------- -
LM
Countnumber
Countnumber
LM
LM
Result
Result
INDUSTRIAL TEMPERATURE
×
×
×
×
2
2
5
5
2
2
×
×
×
×
π
π
8192
8192






+
+
3.14
3.17