IDT821054APF IDT, Integrated Device Technology Inc, IDT821054APF Datasheet - Page 28

• Manufacturer Part Number: IDT821054APF
• Description: IC PCM CODEC QUAD MPI 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054APF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054APF

IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
3.4.3
LREG1: Coefficient Selection, Read/Write (00H/80H)
LREG2: Local Loopback Control and SLIC Input Interrupt Enable, Read/Write (01H/81H)
LOCAL REGISTERS LIST
The Coefficient Select bits (CS[7:0]) are used to control digital filters and function blocks on each channel. The digital filters include
Impedance Matching Filter, Echo Cancellation Filter, High-Pass Filter, Gain for Impedance Scaling, Gain in the Transmit/Receive Path
and Frequency Response Correction in the Transmit/Receive Path. See
Impedance Matching Filter and Gain for Impedance Scaling are working together to adjust the impedance. So the CS[0] and CS[2] bits
should be set to the same value to ensure proper operation.
CS[7] = 0: The Digital Gain Filter in the Receive path (GRX) is disabled (default);
CS[7] = 1: The Digital Gain in the Receive path (GRX) is programmed by the Coe-RAM.
CS[6] = 0: The Frequency Response Correction filter in the Receive path (FRR) is disabled (default);
CS[6] = 1: The coefficient of the Frequency Response Correction filter in the Receive path (FRR) is programmed by the Coe-RAM.
CS[5] = 0: The Digital Gain Filter in the Transmit path (GTX) is disabled (default);
CS[5] = 1: The Digital Gain in the Transmit path (GTX) is set by the Coe-RAM.
CS[4] = 0: The Frequency Response Correction filter in the Transmit path (FRX) is disabled (default);
CS[4] = 1: The coefficient of the Frequency Response Correction filter in the Transmit path (FRX) is programmed by the Coe-RAM.
CS[3] = 0: The High-Pass Filter (HPF) is bypassed/disabled;
CS[3] = 1: The High-Pass Filter (HPF) is enabled (default).
CS[2] = 0: The Gain for Impedance Scaling filter (GIS) is disabled (default);
CS[2] = 1: The coefficient of the Gain for Impedance Scaling filter (GIS) is programmed by the Coe-RAM.
CS[1] = 0: The Echo Cancellation Filter (ECF) is disabled (default);
CS[1] = 1: The coefficient of the Echo Cancellation Filter (ECF) is programmed by the Coe-RAM.
CS[0] = 0: The Impedance Matching Filter (IMF) is disabled (default);
CS[0] = 1: The coefficient of the Impedance Matching Filter (IMF) is programmed by the Coe-RAM.
The SLIC Input Interrupt Enable bits IE[4:0] enable or disable the interrupt signal on each channel.
IE[4] = 0: Interrupt disabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be ignored (default);
IE[4] = 1: Interrupt enabled. The interrupt generated by changes of SB3 (when SB3 is selected as an input) will be recognized.
IE[3] = 0: Interrupt disabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be ignored (default);
IE[3] = 1: Interrupt enabled. The interrupt generated by changes of SB2 (when SB2 is selected as an input) will be recognized.
IE[2] = 0: Interrupt disabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be ignored (default);
IE[2] = 1: Interrupt enabled. The interrupt generated by changes of SB1 (when SB1 is selected as an input) will be recognized.
IE[1] = 0: Interrupt disabled. The interrupt generated by changes of SI2 will be ignored (default);
IE[1] = 1: Interrupt enabled. The interrupt generated by changes of SI2 will be recognized.
IE[0] = 0: Interrupt disabled. The interrupt generated by changes of SI1 will be ignored (default);
IE[0] = 1: Interrupt enabled. The interrupt generated by changes of SI1 will be recognized.
Command
Command
I/O data
I/O data
CS[7]
R/W
R/W
IE[4]
b7
b7
CS[6]
IE[3]
b6
b6
0
0
CS[5]
IE[2]
b5
b5
0
0
CS[4]
IE[1]
28
b4
b4
0
0
CS[3]
IE[0]
b3
b3
Figure - 4 on page 11
0
0
DLB_PCM
CS[2]
b2
b2
0
0
for details. It should be noted that the
ALB_1BIT
CS[1]
b1
b1
INDUSTRIAL TEMPERATURE
0
0
DLB_1BIT
CS[0]
b0
b0
0
1