SGTL5000XNLA3 Freescale Semiconductor, SGTL5000XNLA3 Datasheet - Page 56

• Manufacturer Part Number: SGTL5000XNLA3
• Description: IC AUDIO CODEC STEREO 20-QFN
• Manufacturer: Freescale Semiconductor
• Type: Stereo Audior

Specifications of SGTL5000XNLA3

• Data Interface: I²C, Serial, SPI™
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 90 / 100
• Voltage - Supply, Analog: 1.62 V ~ 3.6 V
• Voltage - Supply, Digital: 1.1 V ~ 2 V, 1.62 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SGTL5000
56
BITS
BITS
15
5:4
3:2
15
8
7
6
1
0
14
SCLKFREQ
I2S_MODE
7.0.0.5.
SCLK_INV
LRALIGN
FIELD
LRPOL
FIELD
RSVD
DLEN
13
MS
12
CHIP_SSS_CTRL
RW RESET
RW RESET
RW
RW
RW
RW
RW
RW
RW
RW
11
0x0
0x0
0x0
0x1
0x0
0x0
0x0
0x0
10
Sets frequency of I2S_SCLK when in master mode (MS=1).
When in slave mode (MS=0), this field must be set
appropriately to match SCLK input rate.
0x0 = 64Fs
0x1 = 32Fs - Not supported for RJ mode (I2S_MODE = 1)
Configures master or slave of I2S_LRCLK and I2S_SCLK.
0x0 = Slave: I2S_LRCLK and I2S_SCLK are inputs
0x1 = Master: I2S_LRCLK and I2S_SCLK are outputs
NOTE: If the PLL is used (CHIP_CLK_CTRL-
>MCLK_FREQ==0x3), the SGTL5000 must be a master of the
I2S port (MS==1)
Sets the edge that data (input and output) is clocked in on for
I2S_SCLK
0x0 = data is valid on rising edge of I2S_SCLK
0x1 = data is valid on falling edge of I2S_SCLK
I2S data length
0x0 = 32 bits (only valid when SCLKFREQ=0), not valid for
Right Justified Mode
0x1 = 24 bits (only valid when SCLKFREQ=0)
0x2 = 20 bits
0x3 = 16 bits
Sets the mode for the I2S port
0x0 = I2S mode or Left Justified (Use LRALIGN to select)
0x1 = Right Justified Mode
0x2 = PCM Format A/B
0x3 = RESERVED
I2S_LRCLK Alignment to data word. Not used for Right
Justified mode
0x0 = Data word starts 1 I2S_SCLK delay after I2S_LRCLK
transition (I2S format, PCM format A)
0x1 = Data word starts after I2S_LRCLK transition (left
justified format, PCM format B)
I2S_LRCLK Polarity when data is presented.
0x0 = I2S_LRCLK = 0 - Left, 1 - Right
1x0 = I2S_LRCLK = 0 - Right, 1 - Left
The left subframe should be presented first regardless of the
setting of LRPOL.
9
Reserved
8
7
0x000A
6
DEFINITION
DEFINITION
5
4
SGTL5000 EA2 DS-0-3
3
2
1
0