AD1981AJST Analog Devices Inc, AD1981AJST Datasheet
AD1981AJST
Specifications of AD1981AJST
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AD1981AJST Summary of contents
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MIC PREAMP AD1981A MIC_IN G AUX PHONE_IN CD_L CD CD_GND DIFF AMP CD_R LINE_IN HP_OUT_L LINE_OUT_L M A MONO_OUT M A LINE_OUT_R HP_OUT_R HP A KEY GAIN A = ATTENUATE M ...
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AD1981A–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25°C Digital Supply ( Analog Supply ( Sample Rate ( kHz S Input Signal 1008 Hz Analog Output Pass Band 20 Hz ...
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SPECIFICATIONS Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) Dynamic Range (–60 dB Input THD+N Referenced to Full Scale, A-Weighted) Signal-to-Intermodulation Distortion (CCIF Method) 1 ADC Crosstalk Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read ...
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AD1981A–SPECIFICATIONS Parameter Set Bits 3 POWER-DOWN STATES (Fully Active) (No Bits Value) ADC PR0 DAC PR1 ADC + DAC PR1, PR0 Mixer PR2 ADC + Mixer PR2, PR0 DAC + Mixer PR2, PR1 ADC + DAC + Mixer PR2, PR1, ...
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... Digital Input Voltage . . . . . . . . . . . . . –0 Analog Input Voltage . . . . . . . . . . . . –0 Ambient Temperature Range (Operating 0°C to 70°C Model AD1981AJST ST = Thin Quad Flatpack CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1981A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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AD1981A CONNECT PIN CONFIGURATION DD1 PIN 1 XTL_IN 2 IDENTIFIER XTL_OUT SS1 SDATA_OUT 5 AD1981A BIT_CLK 6 TOP VIEW DV ...
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Pin No. Mnemonic DIGITAL I/O 2 XTL_IN 3 XTL_OUT 5 SDATA_OUT 6 BIT_CLK 8 SDATA_IN 10 SYNC RESET 11 48 SPDIF CHIP SELECTS (These pins can also be used to select an external clock. See Table II.) ID0 45 ID1 ...
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AD1981A Reg Name D15 D14 D13 00h Reset X SE4 SE3 02h Master Volume 04h Headphones Volume HPM X X 06h Mono Volume MVM X X 0Ch Phone Volume PHM X X 0Eh Mic Volume MCM X ...
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Reg Num Name D15 D14 D13 D12 D11 D10 D9 00h Reset X SE4 SE3 SE2 SE1 SE0 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 0090h Writing any value to this register performs a register reset, which ...
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AD1981A Reg Num Name D15 D14 D13 D12 04h Headphones Volume HPM X NOTES 1 This register controls the headphone volume controls for both stereo channels and mute bit. Each volume subregister contains 5 bits, generating 32 volume levels with ...
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PHV[4:0] Phone Volume: Allows setting the phone volume attenuator in 32 volume levels. The LSB represents 1.5 dB, and the range is + –34.5 dB. The default value with mute bit enabled. PHM Phone Mute: ...
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AD1981A Reg Num Name D15 D14 D13 D12 16h AUX Volume LAV4 LAV3 LAV2 LAV1 LAV0 RM For AC ‘97 compatibility, Bit D7 (RM) is only available by setting the MSPLT bit Register 76h. The MSPLT bit ...
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RS1...RS0 LS1...LS0 Reg Num Name D15 D14 D13 D12 D11 1Ch Record Gain For AC ‘97 compatibility, Bit D7 (RM) is ...
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AD1981A Reg Num Name D15 Power-Down Cntrl/Stat 26h EAPD PR6 PR5 PR4 PR3 PR2 PR1 PR0 X NOTES The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for ...
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VRA Variable Rate PCM Audio Support: (read-only) This bit returns a “1” when read to indicate that variable rate PCM audio is supported. SPDIF SPDIF Support: (read-only) This bit returns a “1” when read to indicate that SPDIF transmitter is ...
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AD1981A AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments CODEC ID Function 00 2-Ch Primary w/SPDIF 00 4-Ch Primary w/SPDIF 00 6-Ch Primary w/SPDIF 01 +2-Ch Secondary w/SPDIF 01 +4-Ch Secondary w/SPDIF 10 +2-Ch Secondary w/SPDIF 10 +4-Ch Secondary w/SPDIF ...
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Reg. Num. Name D15 D14 60h EQCTRL EQM MAD LBEN X Register 60h is a read/write register that controls the equalizer functionality and data setup. The register also contains the biquad and coefficient address pointer, which is used in conjunction ...
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AD1981A CHS Channel Select: CHS = 0 Selects Left Channel Coefficients Data Block CHS = 1 Selects Right Channel Coefficients Data Block SYM Symmetry: When set to “1,” this bit indicates that the left and right channel coefficients are equal. ...
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JS0INT Indicates Pin JS0 has generated an interrupt. Remains set until the software services JS0 interrupt, i.e., JS0 ISR, should clear this bit by writing a “0” to it. Note that the interrupt to the system is actually an OR ...
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AD1981A REF JS1 HEADPHONE FMUTE = Output is forced to mute independent of the respective volume register setting. ACTIVE = Output is not muted and its status is dependent on the respective volume register setting. OUT = Nothing plugged into ...
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REGM0 Master Codec Register Mask REGM1 Slave 1 Codec Register Mask REGM2 Slave 2 Codec Register Mask SLOT16 Enable 16-Bit Slot Mode. SLOT16 makes all AC link slots 16 bits in length, formatted into 16 slots. This is a preferred ...
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AD1981A Reg Num Name D15 D14 D13 D12 D11 D10 D9 D8 7Eh Vendor ID2 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5372h T[7:0] This register is ASCII encoded to ‘S’ ...
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OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 48-Lead Thin Plastic Quad (LQFP) (ST-48) 1.60 (0.0630) MAX GAGE PLANE 0.25 (0.0098) 9.00 (0.3543) BSC SQ 0.75 (0.0295) 0.60 (0.0236) 36 0.45 (0.0177) 37 SEATING PLANE TOP VIEW (PINS DOWN) VIEW ...
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