AD1981AJST Analog Devices Inc, AD1981AJST Datasheet - Page 16

• Manufacturer Part Number: AD1981AJST
• Description: IC CODEC STEREO MICPREAMP 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1981AJST

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 4 / 2
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 90
• Voltage - Supply, Analog: 4.65 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1981A
CODEC ID
00
00
00
01
01
10
10
11
SR[15:0]
SR[15:0]
PRO
/AUD
COPY
PRE
CC[6:0]
L
SPSR[1:0]
V
Reg Num Name
Reg. Num. Name
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
Reg Num Name
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case).
This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz.
With the exception of V, this register should only be written to when the SPDIF transmitter is disabled (SPDIF bit in Register 2Ah is “0”). This
ensures that control and status information start up correctly at the beginning of SPDIF transmission.
2Ch
32h
3Ah
PCM Front DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
PCM L/R ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 BB80h
SPDIF Control
Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments. If “0”
is written to VRA, then the sample rate is reset to 48k.
Sample Rate: The sampling frequency range is from 7 kHz (1B58h) to 48 kHz (BB80h) in 1 Hz increments.
If “0” is written to VRA, then the sample rate is reset to 48k.
Professional: “1” indicates professional use of channel status, “0” indicates consumer.
Non-Audio: “1” indicates data is non-PCM format, “0” data is PCM.
Copyright: “1” indicates copyright is asserted, “0” copyright is not asserted.
Pre-Emphasis: “1” indicates filter pre-emphasis is 50/15 msec, “0” pre-emphasis is none.
Category Code: Programmed according to IEC standards, or as appropriate.
Generation Level: Programmed according to IEC standards, or as appropriate.
SPDIF Transmit Sample Rate:
SPSR[1:0] = “00” Transmit Sample Rate = 44.1 kHz
SPSR[1:0] = “01” Reserved
SPSR[1:0] = “10” Transmit Sample Rate = 48 kHz (Reset Default)
SPSR[1:0] = “11” Not Supported
Validity: This bit affects the “Validity” flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the
SPDIF transmitter to maintain connection during error or mute conditions.
V = 1 Each SPDIF subframe (L + R) has Bit 28 set to “1.” This tags both samples as invalid.
V = 0 Each SPDIF subframe (L + R) has Bit 28 set to “0” for valid data and “1” for invalid data (error condition).
Note that when V = 0, asserting the VFORCE bit (D15) in Register 2Ah (Ext’d Audio Stat/Ctrl) will force the
“Validity” flag low, marking both samples as valid.
Function
2-Ch Primary w/SPDIF
4-Ch Primary w/SPDIF
6-Ch Primary w/SPDIF
+2-Ch Secondary w/SPDIF
+4-Ch Secondary w/SPDIF
+2-Ch Secondary w/SPDIF
+4-Ch Secondary w/SPDIF
+2-Ch Secondary w/SPDIF
D15 D14
V
AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
D15
D15
X SPSR1 SPSR0 L
D13
D14
D14
PCM Front DAC Rate Register (Index 2Ch)
PCM ADC Rate Register (Index 32h)
D13
SPDIF Control Register (Index 3Ah)
D12 D11 D10 D9
D13
SPSA = 00
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
D12
D12
CC6 CC5 CC4 CC3 CC2 CC1 CC0 PRE COPY /AUD PRO 2000h
D11
D11
D10
D10
SPSA = 01
7 and 8 [default]
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
D8
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default
D7
D6
D5
SPSA = 10
6 and 9
6 and 9 [default]
6 and 9
6 and 9 [default]
6 and 9
6 and 9 [default]
6 and 9
6 and 9
D4
D3
D2
SPSA = 11
10 and 11
10 and 11
10 and 11 [default]
10 and 11 [default]
10 and 11 [default]
10 and 11 [default]
D1
D0 Default