MCP2515-I/SO Microchip Technology, MCP2515-I/SO Datasheet - Page 6

• Manufacturer Part Number: MCP2515-I/SO
• Description: IC CAN CONTROLLER W/SPI 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2515-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 2.7V To 5.5V
• Driver Case Style: SOIC
• No. Of Pins: 18
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Supply Voltage Min: 2.7V
• Rohs Compliant: Yes
• Clock Frequency: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP2515
1.5
The CAN protocol engine combines several functional
blocks, shown in Figure 1-4 and described below.
1.5.1
The heart of the engine is the Finite State Machine
(FSM). The FSM is a sequencer that controls the
sequential data stream between the TX/RX shift
register, the CRC register and the bus line. The FSM
also controls the Error Management Logic (EML) and
the parallel data stream between the TX/RX shift
registers and the buffers. The FSM ensures that the
processes of reception, arbitration, transmission and
error-signaling are performed according to the CAN
protocol. The automatic retransmission of messages
on the bus line is also handled by the FSM.
1.5.2
The Cyclic Redundancy Check register generates the
Cyclic Redundancy Check (CRC) code, which is
transmitted after either the Control Field (for messages
with 0 data bytes) or the Data Field and is used to
check the CRC field of incoming messages.
FIGURE 1-4:
DS21801C-page 6
RX
CAN Protocol Engine
PROTOCOL FINITE STATE
MACHINE
CYCLIC REDUNDANCY CHECK
Sample<2:0>
Decision
Majority
Receive<7:0>
RecData<7:0>
CAN PROTOCOL ENGINE BLOCK DIAGRAM
BusMon
Interface to Standard Buffer
Bit Timing Logic
CRC<14:0>
Comparator
SAM
(Transmit<5:0>, Receive<7:0>)
TrmData<7:0>
Transmit<7:0>
StuffReg<5:0>
Comparator
Preliminary
Shift<14:0>
1.5.3
The Error Management Logic is responsible for the
fault confinement of the CAN device. Its two counters,
the Receive Error Counter (REC) and the Transmit
Error
decremented by commands from the bit stream
processor. According to the values of the error
counters, the CAN controller is set into the states error-
active, error-passive or bus-off.
1.5.4
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus related bit timing according to the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard syn-
chronization) and on any further recessive-to-dominant
bus line transition if the CAN controller itself does not
transmit a dominant bit (resynchronization). The BTL
also provides programmable time segments to
compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. The programming of the BTL
depends on the baud rate and external physical delay
times.
Counter
ERROR MANAGEMENT LOGIC
BIT TIMING LOGIC
Transmit Logic
(TEC),
Error Counter
Error Counter
Rec/Trm Addr.
Transmit
Receive
Protocol
 2004 Microchip Technology Inc.
FSM
are
incremented
TX
ErrPas
BusOff
SOF
REC
TEC
and