CY7C63803-SXC Cypress Semiconductor Corp, CY7C63803-SXC Datasheet - Page 40

• Manufacturer Part Number: CY7C63803-SXC
• Description: IC USB PERIPHERAL CTRLR 16-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Interface ICr

Specifications of CY7C63803-SXC

• Package / Case: 16-SOIC (3.9mm Width)
• Controller Type: USB Peripheral Controller
• Interface: PS2, USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Operating Temperature Range: 0 C to + 70 C
• Propagation Delay Time Ns: 50 ns
• Resistance: 4 Ohms to 12 Ohms
• Supply Current: 10 mA
• Watchdog: Yes
• Operating Supply Voltage: 4.35 V to 5.25 V
• Core Size: 8 Bit
• No. Of I/o's: 14
• Program Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Embedded Interface Type: PS/2, USB
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2914-5; CY7C63803-SXC

Table 14-9. P1.3 Configuration (P13CR) [0x10] [R/W]
Table 14-10. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Table 14-11. P1.7 Configuration (P17CR) [0x14] [R/W]
Table 14-12. P2 Configuration (P2CR) [0x15] [R/W]
Document 38-08035 Rev. *N
This register controls the operation of the P1.3 pin. This register exists in all enCoRe II parts.
The P1.3 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled or disabled, the pin is controlled by the Output Enable bit and the corresponding bit in the
P1 data register.
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain, and
Pull-up Enable control the behavior of the pin.
These registers control the operation of pins P1.4–P1.6, respectively. These registers exist in all enCoRe II parts.
Bit 7: SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
The P1.4–P1.6 GPIO’s threshold is always set to TTL.
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by
the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable
bit and the corresponding bit in the P1 data register.
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain,
and Pull-up Enable control the behavior of the pin.
Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input and output direction
of pins P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input and output direction is NOT automatically
set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode,
pin P1.4 must be configured as an input.
This register controls the operation of pin P1.7. This register only exists in CY7C638(1/2/3)3. The P1.7 GPIO’s threshold is
always set to TTL.
This register only exists in CY7C638(2/3)3. This register controls the operation of pins P2.0–P2.1.
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
Reserved
Reserved
Reserved
SPI Use
R/W
7
–
0
7
0
7
–
0
7
–
0
Int Enable
Int Enable
Int Enable
Int Enable
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
Int Act Low
Int Act Low
Int Act Low
Int Act Low
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
TTL Thresh
3.3V Drive
3.3V Drive
Reserved
R/W
R/W
R/W
4
0
4
0
4
–
0
4
0
Table 15-2 on page
High Sink
High Sink
High Sink
Reserved
R/W
R/W
R/W
3
0
3
0
3
0
3
–
0
42)
Open Drain
Open Drain
Open Drain
Open Drain
R/W
R/W
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
2
0
2
0
Pull-up Enable
Pull-up Enable
Pull-up Enable
Pull-up Enable
R/W
R/W
R/W
R/W
1
0
1
0
1
1
1
0
Output Enable
Output Enable
Output Enable
Output Enable
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R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
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