CY7C63803-SXC Cypress Semiconductor Corp, CY7C63803-SXC Datasheet - Page 45

• Manufacturer Part Number: CY7C63803-SXC
• Description: IC USB PERIPHERAL CTRLR 16-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Interface ICr

Specifications of CY7C63803-SXC

• Package / Case: 16-SOIC (3.9mm Width)
• Controller Type: USB Peripheral Controller
• Interface: PS2, USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Operating Temperature Range: 0 C to + 70 C
• Propagation Delay Time Ns: 50 ns
• Resistance: 4 Ohms to 12 Ohms
• Supply Current: 10 mA
• Watchdog: Yes
• Operating Supply Voltage: 4.35 V to 5.25 V
• Core Size: 8 Bit
• No. Of I/o's: 14
• Program Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Embedded Interface Type: PS/2, USB
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2914-5; CY7C63803-SXC

Table 16-3. Timer Capture 0 Rising (TIO0R) [0x22] [R/W]
Table 16-4. Timer Capture 1 Rising (TIO1R) [0x23] [R/W]
Table 16-5. Timer Capture 0 Falling (TIO0F) [0x24] [R/W]
Table 16-6. Timer Capture 1 Falling (TIO1F) [0x25] [R/W]
Table 16-7. Programmable Interval Timer Low (PITMRL) [0x26] [R]
Document 38-08035 Rev. *N
Bit [7:0]: Capture 0 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TIO0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
Bit [7:0]: Capture 1 Rising [7:0]
This register holds the value of the Free-running Timer when the last rising edge occurred on the TIO1 input in the 8-bit mode.
The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When Capture 0 is in
16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last Capture 0 rising edge.
Bit [7:0]: Capture 0 Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TIO0 input. When Capture 0
is in 8-bit mode, the bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When
Capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer.
Bit [7:0]: Capture 1Falling [7:0]
This register holds the value of the Free-running Timer when the last falling edge occurred on the TIO1 input in the 8-bit mode.
The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register. When capture 0 is in
16-bit mode this register holds the high order 8 bits of the 16-bit timer from the last Capture 0 falling edge.
Bit [7:0]: Prog Interval Timer [7:0]
This register holds the low order byte of the 12-bit programmable interval timer. Reading this register causes the high order byte
to be moved into a holding register allowing an automatic read of all 12 bits simultaneously.
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Default
Field
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
Bit #
R/W
R/W
R/W
R/W
R
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R
6
0
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
R
5
0
5
0
5
0
5
0
5
0
Prog Interval Timer [7:0]
R/W
R/W
Capture 0 Falling [7:0]
R/W
Capture 1 Falling [7:0]
R/W
Capture 0 Rising [7:0]
Capture 1 Rising [7:0]
R
4
0
4
0
4
0
4
0
4
0
R/W
R/W
R/W
R/W
R
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
CY7C63310, CY7C638xx
R
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R
1
0
1
0
1
0
1
0
1
0
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R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
0
0
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