CY7C63801-PXC Cypress Semiconductor Corp, CY7C63801-PXC Datasheet - Page 26
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CY7C63801-PXC
Manufacturer Part Number
CY7C63801-PXC
Description
IC USB PERIPHERAL CTRLR 16-DIP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C63801-PXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
MDIP
Mounting
Through Hole
Pin Count
16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
10.1.1 Interval Timer Clock (ITMRCLK)
The Interval Timer Clock (TITMRCLK), is sourced from an
external clock, the Internal 24 MHz Oscillator, the Internal 32 kHz
Low power Oscillator, or the Timer Capture clock. A
programmable prescaler of 1, 2, 3 or 4 then divides the selected
source. The 12-bit Programmable Interval Timer is a simple
down counter with a programmable reload value. It provides a
1 μs resolution by default. When the down counter reaches zero,
the next clock is spent reloading. The reload value is read and
written while the counter is running, but the counter must not
unintentionally reload when the 12-bit reload value is only
partially stored, that is, between the two writes of the 12-bit value.
The programmable interval timer generates an interrupt to the
CPU on each reload.
The parameters to be set show up on the device editor view of
PSoC Designer when the enCoRe II Timer User Module is
placed. The parameters are PITIMER_Source and
PITIMER_Divider. The PITIMER_Source is the clock to the timer
and the PITMER_Divider is the value the clock is divided by.
Document 38-08035 Rev. *N
S y s te m
T im e r
C lo c k
C lo c k
Figure 10-2. Programmable Interval Timer Block Diagram
C o n fig u ra tio n
S ta tu s a n d
C o n tro l
1 2 -b it d o w n
The interval register (PITMR) holds the value that is loaded into
the PIT counter on terminal count. The PIT counter is a down
counter.
The Programmable Interval Timer resolution is configurable. For
example:
TCAPCLK divide by x of CPU clock (for example, TCAPCLK
divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz.)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 μs.)
10.1.2 Timer Capture Clock (TCAPCLK)
The Timer Capture clock is sourced from an external clock,
Internal 24 MHz Oscillator or the Internal 32 kHz Low power
Oscillator. A programmable pre-scaler of 2, 4, 6, or 8 then divides
the selected source.
c o u n te r
re lo a d
1 2 -b it
v a lu e
c o u n te r
re lo a d
1 2 -b it
CY7C63310, CY7C638xx
C o n tro lle r
In te rru p t
Page 26 of 86
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