CY7C63801-PXC Cypress Semiconductor Corp, CY7C63801-PXC Datasheet - Page 46

• Manufacturer Part Number: CY7C63801-PXC
• Description: IC USB PERIPHERAL CTRLR 16-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63801-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 16-8. Programmable Interval Timer High (PITMRH) [0x27] [R]
Table 16-9. Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Table 16-10. Programmable Interval Reload High (PIRH) [0x29] [R/W]
Document 38-08035 Rev. *N
Bit [7:4]: Reserved
Bit [3:0]: Prog Internal Timer [11:8]
This register holds the high order nibble of the 12-bit programmable interval timer. Reading this register returns the high order
nibble of the 12-bit timer at the instant that the low order byte was last read.
Bit [7:0]: Prog Interval [7:0]
This register holds the lower 8 bits of the timer. When writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
Bit [7:4]: Reserved
Bit [3:0]: Prog Interval [11:8]
This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write the lower byte first then the higher
nibble.
Read/Write
Read/Write
Read/Write
Default
Default
Default
Field
Field
Field
Bit #
Bit #
Bit #
S y s t e m
C l o c k
C l o c k
T i m e r
R/W
7
–
0
7
0
7
–
0
R/W
6
–
0
6
0
6
–
0
Figure 16-2. Programmable Interval Timer Block Diagram
C o n f i g u r a t i o n
S t a t u s a n d
Reserved
Reserved
C o n t r o l
R/W
5
–
0
5
0
5
–
0
R/W
4
–
0
4
0
4
–
0
Prog Interval [7:0]
1 2 - b i t d o w n
c o u n t e r
r e l o a d
1 2 - b i t
v a l u e
R/W
R/W
R
3
0
3
0
3
0
Prog Interval Timer [11:8]
R/W
R/W
c o u n t e r
CY7C63310, CY7C638xx
R
2
0
2
0
2
0
r e l o a d
Prog Interval[11:8]
1 2 - b i t
R/W
R/W
R
1
0
1
0
1
0
C o n t r o l l e r
I n t e r r u p t
Page 46 of 86
R/W
R/W
R
0
0
0
0
0
0
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