CP2201-GM Silicon Laboratories Inc, CP2201-GM Datasheet - Page 49
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CP2201-GM
Manufacturer Part Number
CP2201-GM
Description
IC ETH CTRLR SNGL-CHIP 28QFN
Manufacturer
Silicon Laboratories Inc
Specifications of CP2201-GM
Package / Case
48-TQFP, 48-VQFP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
Parallel/Serial
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
75mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Ethernet Connection Type
1000BASE-T or 100BASE-T or 10BASE-T
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Standard Supported
IEEE 802.3
Data Rate
10 Mbps or 100 Mbps or 1000 Mbps
Maximum Operating Temperature
+ 85 C
No. Of Ports
1
Ethernet Type
IEEE 802.3
Interface Type
Parallel
Supply Current
60mA
Supply Voltage Range
3.1V To 3.6V
Operating Temperature Range
-40°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1326 - KIT REF DESIGN PWR OVER ETHERNET336-1316 - KIT EVAL FOR CP2201 ETH CTRLR
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1313
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CP2201-GM
Manufacturer:
SiliconL
Quantity:
48
Part Number:
CP2201-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
11.5. Transmit Status and Control Registers
The CP2200 transmit interface is controlled and managed through the registers in Table 14. After each packet is
transmitted, information about the last transmitted packet can be obtained from the 52-bit transmit status vector
accessible through the TXSTA0 — TXSTA6 registers. The transmit status vector is described in Table 15.
TXCN
TXBUSY
TXPAUSEH
TXPAUSEL
TXSTARTH
TXSTARTL
TXENDH
TXENDL
TXAUTOWR Transmit Data AutoWrite
TXSTA6
TXSTA5
TXSTA4
TXSTA3
TXSTA2
TXSTA1
TXSTA0
Register
Transmit Control
Transmit Pause High and Low Bytes
Transmit Data Starting Address High
and Low Bytes
Transmit Data Ending Address High
and Low Bytes
Transmit Status Vector
Transmit Busy Indicator
Table 14. Transmit Status and Control Register Summary
Long Name
Rev. 1.0
Address
0x5A
0x5C
0x5D
0x5E
0x53
0x55
0x56
0x59
0x57
0x58
0x03
0x5F
0x60
0x61
0x62
0x54
Contains the transmit configuration option over-
ride bits and the TXGO bit used to start packet
transmission.
Read-only register returning 0x01 when transmit
interface is currently transmitting a packet and
0x00 when transmit interface is not transmitting.
16-bit pause value used for PAUSE packet
transmission. The pause value is in units of 512
bit times (51.2
Starting address of outgoing packet in the trans-
mit buffer. Packets added to the transmit buffer
must start at 0x0000.
Address of last byte added to the transmit
buffer. This register is managed by hardware.
Writes to this register add a byte to the transmit
buffer, set TXEND to the address of the written
byte, and increment TXSTART.
52-bit transmit status vector containing informa-
tion about the last transmitted packet including
collision count, successful transmission, total
bytes transmitted, etc.
μ
s).
Description
CP2200/1
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