KSZ8851SNL TR Micrel Inc, KSZ8851SNL TR Datasheet - Page 45

• Manufacturer Part Number: KSZ8851SNL TR
• Description: IC CTLR MAC/PHY NON-PCI 32-MLF
• Manufacturer: Micrel Inc

Specifications of KSZ8851SNL TR

• Controller Type: Ethernet Controller, MAC/PHY
• Interface: Bus
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-MLF®, QFN
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-3293 - BOARD EVALUATION KSZ8851SNL
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3299-2

0x3C – 0x3F: Reserved
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1
This register contains the expected CRC values of the Wake up frame 1 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in
the wake up byte mask registers.
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0
This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte
of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1.
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1.
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 1. Setting bit 15 selects the 48th byte of the Wake up frame 1.
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3
This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 1. Setting bit 15 selects the 64th byte of the Wake up frame 1.
August 2009
Micrel, Inc.
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-0
Bit
15-0
Default Value
0x0000
Default Value
0x0000
Default Value
0x0000
Default Value
0x0000
Default Value
0x0000
R/W
RW
R/W
RW
R/W
RW
R/W
RW
R/W
RW
Description
WF1CRC0
Wake-up frame 1 CRC (lower 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Description
WF1CRC1
Wake-up frame 1 CRC (upper 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Description
WF1BM0
Wake-up frame 1 Byte Mask 0.
The first 16 bytes mask of a Wake-up frame 1 pattern.
Description
WF1BM1
Wake-up frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake-up frame 1 pattern.
Description
WF1BM2
Wake-up frame 1 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 1 pattern.
45
KSZ8851SNL/SNLI
M9999-083109-2.0