ISP1761BE-S ST-Ericsson Inc, ISP1761BE-S Datasheet - Page 46

• Manufacturer Part Number: ISP1761BE-S
• Description: IC USB CONTROLLER 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1761BE-S

• Controller Type: USB Peripheral Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: ISP1761BE,551; Q2203522

NXP Semiconductors
Table 36.
Table 37.
Table 38.
ISP1761_5
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcChipID - Host Controller Chip Identifier register (address 0304h) bit description
HcScratch - Host Controller Scratch register (address 0308h) bit description
SW Reset - Software Reset register (address 030Ch) bit allocation
Symbol
SCRATCH[31:0]
Symbol
CHIPID[31:0]
8.3.2 HcChipID register
8.3.3 HcScratch register
8.3.4 SW Reset register
R/W
R/W
31
23
0
0
Table 35.
Read this register to get the ID of the ISP1761. This upper word of the register contains
the hardware version number and the lower word contains the chip ID.
bit description of the register.
This register is for testing and debugging purposes only. The value read back must be the
same as the value that was written. The bit description of this register is given in
Table 38
Bit
2
1
0
Access
R
R/W
R/W
30
22
0
0
Access
R/W
shows the bit allocation of the register.
Symbol
INTR_POL
INTR_LEVEL
GLOBAL_INTR_EN
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description
Value
0001 1761h
R/W
R/W
29
21
0
0
Value
0000 0000h
…continued
Rev. 05 — 13 March 2008
Description
Chip ID: This register represents the hardware version number
(0001h) and the chip ID (1761h) for the host controller.
Description
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
Global Interrupt Enable: This bit must be set to logic 1 to enable
IRQ signal assertion.
0 — IRQ assertion disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion enabled. IRQ will be asserted according to the
HcInterruptEnable register, and events setting and occurrence.
R/W
R/W
28
20
0
0
reserved
reserved
Description
Scratch: For testing and debugging purposes
[1]
[1]
R/W
R/W
27
19
0
0
R/W
R/W
26
18
0
0
Hi-Speed USB OTG controller
R/W
R/W
25
17
Table 36
0
0
© NXP B.V. 2008. All rights reserved.
ISP1761
shows the
Table
R/W
R/W
45 of 163
24
16
0
0
37.