Z16C3510VSG Zilog, Z16C3510VSG Datasheet - Page 139

• Manufacturer Part Number: Z16C3510VSG
• Description: IC 10MHZ Z8500 CMOS ISCC 68-PLCC
• Manufacturer: Zilog
• Series: IUSC™r

Specifications of Z16C3510VSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: USB
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM011001-0601
The primary chip in this logic is the Shift register (HCT164),
which generates /INTACK, /SCCRD and /WAIT. During
I/O and normal memory access cycles, the Shift Register
(HCT164) remains cleared because the /M1 signal is
inactive during the opcode fetch cycle. Since the Shift
Register output is Low, control of /SCCRD and /WAIT is by
Normally, an Interrupt Acknowledge cycle appears from
the Z180 during /M1 and /IORQ active (which is detected
on the third rising edge of PHI after T1). To get an early
sign of an Interrupt Acknowledge cycle, the Shift register
decodes an active /M1. This is during the presence of an
inactive /MREQ on the rising edge of T2.
During an Interrupt Acknowledge cycle, the /INTACK
signal is generated on the rising edge of T2. Since it is the
presence of /INTACK and an active SCCRD that gates the
interrupt vector onto the data bus, the logic also generates
/SCCRD at the proper time. The timing parameter of
concern
USING EPLD
Figure 16a and Figure 16b show the logic using either
EPLD or the circuit of this system. The EPLD is ALTERA
610 which is a 24-Pin EPLD. The method to convert
here
VECTOR
/INTACK
/SCCRD
/IORQ
/WAIT
/M1
is
TdIAi(RD)
10
T1
Figure 15. SCC Interrupt Acknowledge Cycle Timing
60 ns max
[/INTACK
SCC
T2
15
to
T
WA
28
/RD
SCC
50 ns max
13
other system logic and gated through the NOR gate
(HCT27). During I/O and normal memory access cycles,
/SCCRD and /SCCWR are generated from the system /RD
and /WR signals, respectively. The generation is by the
logic at the top of Figure 15.
(Acknowledge) Low delay]. This time delay allows the
interrupt daisy chain to settle so the device requesting the
interrupt places its interrupt vector onto the data bus.
The Shift Register allows enough time delay from the
generation of /INTACK before it generates /SCCRD.
During this delay, it places the Z180 into a Wait state until
the valid interrupt vector is placed onto the data bus. If the
time between these two signals is not enough for daisy
chain settling, more time is added by taking /SCCRD and
/WAIT from a later position on the Shift Register. If there is
a requirement for more wait states, the time is calculated
by PHI cycles.
random gate logic to EPLD is to disassemble MSIs’ logic
into SSI level, and then simplify the logic.
T WA
120 ns max
The Z180™ Interfaced with the SCC at MHZ
T WA
SCC
10
60 ns max
T WA
50 ns max
Valid Data
15
14
29
T3
> 25 ns
Application Note
7-19
7