IDT82V2108BB IDT, Integrated Device Technology Inc, IDT82V2108BB Datasheet - Page 265
IDT82V2108BB
Manufacturer Part Number
IDT82V2108BB
Description
IC FRAMER T1/J1/E1 8CH 144-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108BB
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
144-BGA
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
82V2108BB
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IDT82V2108
T1 / J1 RHDLC #1, #2 Configuration (054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H)
J1-00DH).
MEN, MM:
TR:
new HDLC searching.
EN:
FIFO buffer, clear the interrupts and initiate a new HDLC searching.
Programming Information
MEN
Bit Name
Default
Bit No.
0
1
1
Type
Selection of the RHDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the RHDLCSEL[1:0] (b7~6, T1/
The MEN & MM define the address matching mode:
= 0: Normal operation.
= 1: Force the RHDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts and initiate a
This bit is clear to ‘0’ after a rising and falling edge occur on the internal clock or after the register is read.
= 0: Disabled the operation of the RHDLC block and all the FIFO buffer and interrupts are cleared.
= 1: Enabled the operation of the RHDLC block and the HDLC opening flag will be searched immediately.
If the EN is set from logic 1 to logic 0 and back to logic 1, the RHDLC will immediately terminate the reception of the current data frame, empty the
MM
X
0
1
No address matching is needed. All the HDLC data is stored in the FIFO.
The HDLC data is stored in the FIFO when the first byte is all ‘One’s or the same as the setting in the PA[7:0] (b7~0, T1/J1- 058H) or the SA[7:0]
(b7~0, T1/J1-059H).
The HDLC data is stored in the FIFO when the most significant 6 bits in the first byte are all ‘One’s or the same as the setting in the PA[7:2]
(b7~2, T1/J1-058H) or the SA[7:2] (b7~2, T1/J1-059H).
7
6
Reserved
5
4
Address Matching Mode
255
MEN
R/W
3
0
R/W
MM
2
0
T1 / E1 / J1 OCTAL FRAMER
R/W
TR
1
0
March 5, 2009
R/W
EN
0
0
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