IDT82V2108PXG IDT, Integrated Device Technology Inc, IDT82V2108PXG Datasheet - Page 247
IDT82V2108PXG
Manufacturer Part Number
IDT82V2108PXG
Description
IC FRAMER T1/J1/E1 8CH 128-PQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82V2108PX8.pdf
(292 pages)
Specifications of IDT82V2108PXG
Controller Type
T1/E1/J1 Framer
Interface
Parallel
Voltage - Supply
2.97 V ~ 3.63 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
128-MQFP, 128-PQFP
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V2108PXG
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IDT82V2108PXG8
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IDT82V2108
T1 / J1 THDLC #1, #2 Upper Transmit Threshold (035H, 0B5H, 135H, 1B5H, 235H, 2B5H, 335H, 3B5H)
J1-00DH).
UTHR[6:0]:
The transmission will not stop until the last complete packet is transmitted and the THDLC FIFO fill level is below ‘UTHR[6:0] + 1’.
T1 / J1 THDLC #1, #2 Lower Interrupt Threshold (036H, 0B6H, 136H, 1B6H, 236H, 2B6H, 336H, 3B6H)
J1-00DH).
LINT[6:0]:
will be generated. It should be less than the value of the UTHR[6:0] unless both are equal to 00H.
Programming Information
Bit Name
Bit Name
Default
Default
Bit No.
Bit No.
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/
These bits define the upper fill level of the FIFO. Once the fill level exceeds the UTHR[6:0] value, the data stored in the FIFO will start to transmit.
It should be greater than the value of the LINT[6:0] unless both are equal to 00H.
Type
Selection of the THDLC block (#1 or #2) whose registers are visible on the microprocessor interface is done via the THDLCSEL[1:0] (b5~4, T1/
These bits define the fill level of the FIFO that can introduce an interrupt. That is, when the fill level of the FIFO is below the LINT[6:0], an interrupt
Type
Reserved
Reserved
7
7
UTHR[6]
LINT[6]
R/W
R/W
6
0
6
1
UTHR[5]
LINT[5]
R/W
R/W
5
0
5
0
UTHR[4]
LINT[4]
R/W
R/W
4
0
4
0
237
UTHR[3]
LINT[3]
R/W
R/W
3
0
3
0
UTHR[2]
LINT[2]
R/W
R/W
2
0
2
1
T1 / E1 / J1 OCTAL FRAMER
UTHR[1]
LINT[1]
R/W
R/W
1
0
1
1
March 5, 2009
UTHR[0]
LINT[0]
R/W
R/W
0
0
0
1
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