CP82C59A Intersil, CP82C59A Datasheet - Page 7

• Manufacturer Part Number: CP82C59A
• Description: IC CONTROLLER CMOS 28P-DIP
• Manufacturer: Intersil

Specifications of CP82C59A

• Controller Type: CMOS Priority Interrupt Controller
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 1mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -

These events occur in an 8080/8085 system:
1. One or more of the INTERRUPT REQUEST lines
2. The 82C59A evaluates those requests in the priority
3. The CPU acknowledges the lNT and responds with an
4. Upon receiving an lNTA from the CPU group, the highest
5. This CALL instruction will initiate two additional INTA
6. These two INTA pulses allow the 82C59A to release its
7. This completes the 3-byte CALL instruction released by
The events occurring in an 80C86/88/286 system are the
same until step 4.
(IR0 - IR7) are raised high, setting the corresponding IRR
bit(s).
resolver and sends an interrupt (INT) to the CPU, if
appropriate.
INTA pulse.
priority lSR bit is set, and the corresponding lRR bit is
reset. The 82C59A will also release a CALL instruction
code (11001101) onto the 8-bit data bus through D0 - D7.
pulses to be sent to 82C59A from the CPU group.
preprogrammed subroutine address onto the data bus.
The lower 8-bit address is released at the first INTA pulse
and the higher 8-bit address is released at the second
INTA pulse.
the 82C59A. In the AEOI mode, the lSR bit is reset at the
end of the third INTA pulse. Otherwise, the lSR bit
remains set until an appropriate EOI command is issued
at the end of the interrupt sequence.
CASCADE
LINES
7
FIGURE 5. 82C59A STANDARD SYSTEM BUS INTERFACE
ADDRESS BUS (16)
CONTROL BUS
DATA BUS (8)
SLAVE PROGRAM/
ENABLE BUFFER
CAS 0
CAS 1
CAS 2
SP/EN
CS
IRQ
A
7
0
82C59A
82C59A
IRQ
6
D
7
IRQ
4. The 82C59A does not drive the data bus during the first
5. The 80C86/88/286 CPU will initiate a second INTA pulse.
6. This completes the interrupt cycle. In the AEOI mode, the
If no interrupt request is present at step 4 of either sequence
(i.e., the request was too short in duration), the 82C59A will
issue an interrupt level 7. If a slave is programmed on IR bit
7, the CAS lines remain inactive and vector addresses are
output from the master 82C59A.
Interrupt Sequence Outputs
8080, 8085 Interrupt Response Mode
This sequence is timed by three INTA pulses. During the first
lNTA pulse, the CALL opcode is enabled onto the data bus.
First Interrupt Vector Byte Data: Hex CD
During the second INTA pulse, the lower address of the
appropriate service routine is enabled onto the data bus.
5
Call Code
- D
82C59A
INTA pulse.
During this INTA pulse, the appropriate ISR bit is set and
the corresponding bit in the IRR is reset. The 82C59A
outputs the 8-bit pointer onto the data bus to be read by
the CPU.
ISR bit is reset at the end of the second INTA pulse. Oth-
erwise, the ISR bit remains set until an appropriate EOI
command is issued at the end of the interrupt subroutine.
0
INTERRUPT
IRQ
REQUESTS
4
IRQ
RD
D7
3
1
I/OR
WR
IRQ
D6
2
1
I/OW
IRQ
INT
D5
1
0
INT
INTA
IRQ
D4
0
0
INTA
D3
1
D2
1
March 17, 2006
D1
0
FN2784.5
D0
1