USBN9603-28M/NOPB National Semiconductor, USBN9603-28M/NOPB Datasheet - Page 33

• Manufacturer Part Number: USBN9603-28M/NOPB
• Description: IC CONTROLLER USB 28-SOIC
• Manufacturer: National Semiconductor

Specifications of USBN9603-28M/NOPB

• Controller Type: USB 2.0 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Usb Type: Node Controller
• Usb Version: 1.1
• No. Of Ports: 2
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: SOIC
• No. Of Pins: 28
• Rohs Compliant: Yes
• For Use With: USBN9604-HS-EB - KIT NODE CONTROLLER SAMPLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *USBN9603-28M; *USBN9603-28M/NOPB; USBN9603-28M

7.0 Register Set
TX_EV
Transmit Event. This bit is set if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOx or TXUNDRNx)
is set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared when all the TX_DONE bits and
the TXUNDRN bits in each Transmit Status (TXSx) register are cleared.
FRAME
This bit is set if the frame counter is updated with a new value. This can be due to receipt of a valid SOF packet on the USB
or to an artificial update if the frame counter was unlocked or a frame was missed. This bit is cleared when the register is
read.
NAK
Negative Acknowledge. One of the unmasked NAK Event (NAKEV) register bits has been set. This bit is cleared when the
NAKEV register is read.
ULD
Unlock Locked Detected. The frame timer has either entered unlocked condition from a locked condition, or has re-entered
a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH or FNL) register that
is set. This bit is cleared when the register is read.
RX_EV
Receive Event. This bit is set if any of the unmasked bits in the Receive Event (RXEV) register is set. It indicates that a
SETUP or OUT transaction has been completed. This bit is cleared when all of the RX_LAST bits in each Receive Status
(RXSx) register and all RXOVRRN bits in the RXEV register are cleared.
INTR
Master Interrupt Enable. This bit is hardwired to 0 in the Main Event (MAEV) register; the corresponding bit in the Main Mask
(MAMSK) register is the Master Interrupt Enable.
7.1.6
When set to 1, an interrupt is enabled when the respective event in the MAEV register is enabled. Otherwise, interrupt gen-
eration is disabled.
7.1.7
WKUP
Wake-Up Event. This bit is set when a wake-up interrupt is generated and issued on the external INTR pin. The WKUP bit
is read only and cleared when the corresponding wake-up pending bit (PNDUC and/or PNDUSB in the Wake-Up (WKUP)
register) is cleared.
DMA
DMA Event. One of the unmasked bits in the DMA Event (DMAEV) register has been set. The DMA bit is read only and
cleared when the DMAEV register is cleared.
Main Mask Register (MAMSK)
Alternate Event Register (ALTEV)
RESUME
bit 7
CoR
bit 7
0
0
(Continued)
bit 6
0
RESET
bit 6
CoR
0
bit 5
Same Bit Definition as MAEV Register
0
bit 5
SD5
CoR
0
bit 4
0
CoR
bit 4
SD3
r/w
33
0
bit 3
0
EOP
bit 3
CoR
0
bit 2
0
DMA
bit 2
0
r
bit 1
WKUP
0
bit 1
0
r
bit 0
bit 0
res
0
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