MAX3421EETJ+T Maxim Integrated Products, MAX3421EETJ+T Datasheet - Page 22

• Manufacturer Part Number: MAX3421EETJ+T
• Description: IC USB PERIPH/HOST CNTRL 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3421EETJ+T

• Controller Type: USB Peripheral Controller
• Interface: USB/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• For Use With: MAX3421EVKIT-1+ - EVAL KIT FOR MAX3421E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB Peripheral/Host Controller
with SPI Interface
• USB packet PID detection and checking
• CRC check and generation
• Automatic retries in case of errors
• USB packet generation
• NRZI data encoding and decoding
• Bit stuffing and unstuffing
• USB error detection
• USB bus reset, suspend, and wake-up detection
• USB suspend/resume signaling
• Automatic flow control (NAK)
An internal PLL multiplies the 12MHz oscillator signal
by four to produce an internal 48MHz clock. When the
chip is powered down, the oscillator is turned off to
conserve power. When repowered, the oscillator and
PLL require time to stabilize and lock. The OSCOKIRQ
interrupt bit is used to indicate to the SPI master that
the clocking system is stable and ready for operation.
The oscillator and PLL can be turned off by setting the
PWRDOWN bit in the USBCTL (R15) register (see the
Suspend section).
According to USB rev. 2.0 specification, when a USB
host stops sending traffic for at least 3ms to a peripher-
al, the peripheral must enter a power-down state called
SUSPEND. Once suspended, the peripheral must have
enough of its internal logic active to recognize when the
host resumes signaling, or if enabled for remote wake-
up, that the SPI master wishes to signal a resume
event. The following sections titled Suspend and
Wakeup and USB Resume describe how the SPI mas-
ter coordinates with the MAX3421E to accomplish this
power management.
After 3ms of USB bus inactivity, a USB peripheral is
required to enter the USB suspend state and draw no
more than 500µA of V
handled differently depending on whether the
MAX3421E is used as a host or as a peripheral.
In host mode, the MAX3421E suspends the bus by set-
ting SOFKAEN = 0. This stops automatic generation of
the 1ms frame signals (SOF for full speed, keep-alive
for low speed).
22
______________________________________________________________________________________
BUS
current. The suspend state is
Power Management
Suspend in Host Mode
Suspend
PLL
In peripheral mode, after 3ms of USB bus inactivity, the
MAX3421E sets the SUSPIRQ bit in the USBIRQ (R13)
register and asserts the INT output, if SUSPIE = 1 and
IE = 1. The SPI master must do any necessary power-
saving housekeeping and then set the PWRDOWN bit
in the USBCTL (R15) register. This instructs the
MAX3421E to enter a power-down state, in which it
does the following:
• Stops the 12MHz oscillator
• Keeps the INT output active (according to the mode
• Monitors the USB D+ line for a low level
• Monitors the SPI port for any traffic
Note that the MAX3421E does not automatically enter a
power-down state after 3ms of bus inactivity. This
allows the SPI master to perform any preshutdown
tasks before it requests the MAX3421E to enter the
power-down state by setting PWRDOWN = 1.
Wakeup and USB resume are handled differently
depending on whether the MAX3421E is used as a host
or as a peripheral.
After a host has suspended the bus by setting
SOFKAEN = 0, it can resume bus traffic in two ways:
1) The SPI master initiates a host resume operation by
2) The host recognizes a remote wakeup signal from a
The MAX3421E can wake up in three ways while it is a
peripheral in the power-down state:
1) The SPI master clears the PWRDOWN bit in the
2) The SPI master signals a USB remote wakeup by
set in the PINCTL (R17) register)
setting the bit SIGRSM = 1. The MAX3421E asserts
the resume signaling for 20ms, and then asserts the
BUSEVENTIRQ bit. The SPI master then sets
SOFKAEN = 1 to generate the 1ms frame markers
that keep the peripheral alive.
peripheral. The MAX3421E has an interrupt bit for this
purpose called RSMREQIRQ (resume request IRQ).
USBCTL (R15) register (this is also achieved by a
chip reset).
setting the SIGRWU bit in the USBCTL (R15) regis-
ter. When SIGRWU = 1 the MAX3421E restarts the
oscillator and waits for it to stabilize. After the oscil-
lator stabilizes, the MAX3421E drives RESUME sig-
naling (a 10ms K-state) on the bus. The MAX3421E
times this interval to relieve the SPI master of having
to keep accurate time. The MAX3421E also ensures
Wakeup and USB Resume in Peripheral Mode
Wakeup and USB Resume in Host Mode
Wakeup and USB Resume
Suspend in Peripheral Mode