MAX3421EEHJ+T Maxim Integrated Products, MAX3421EEHJ+T Datasheet - Page 23

• Manufacturer Part Number: MAX3421EEHJ+T
• Description: IC USB PERIPH/HOST CNTRL 32TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3421EEHJ+T

• Controller Type: USB Peripheral Controller
• Interface: USB/Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 15mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• For Use With: MAX3421EVKIT-1+ - EVAL KIT FOR MAX3421E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3) The host resumes bus activity. To enable the
The MAX3421E has three reset mechanisms:
• Power-On Reset. This is the most inclusive reset
• Chip Reset. The SPI master can assert a chip
• USB Bus Reset. A USB bus reset is the least
Note: A power-on or chip reset clears the host bit and
puts the MAX3421E into peripheral mode.
At power-on, all register bits except 3 are cleared. The
following 3 bits are set to 1 to indicate that the IN FIFOs
are available for loading by the SPI master (BAV =
buffer available):
• IN3BAVIRQ
• IN2BAVIRQ
• IN0BAVIRQ
Pulling the RES pin low or setting CHIPRES = 1 clears
most of the bits that control USB operation, but keeps
the SPI and pin-control bits unchanged so the interface
between the SPI master and the MAX3421E is not dis-
turbed. Specifically:
• CHIPRES is unchanged. If the SPI master asserted
• CONNECT is unchanged, keeping the device
• General-purpose outputs GPOUT7–GPOUT0
that the RESUME signal begins only after at least
5ms of the bus idle state. When the MAX3421E fin-
ishes its RESUME signaling, it sets the RWUDNIRQ
(remote wake-up done interrupt request) interrupt
flag in the USBIRQ (R13) register. At this time the
SPI master should clear the SIGRWU bit.
MAX3421E to wake up from host signaling, the SPI
master sets the HOSCSTEN (host oscillator start
enable) bit of the USBCTL (R15) register. While in
this mode, if the MAX3421E detects a 1 to 0 transi-
tion on D+, the MAX3421E restarts the oscillator and
waits for it to stabilize.
(sets all internal register bits to a known state).
reset by setting the bit CHIPRES = 1, which has
the same effect as pulling the RES pin low. This
reset clears only some register bits and leaves
others alone.
inclusive (clears the smallest number of bits).
this reset by setting CHIPRES = 1, it removes the
reset by writing CHIPRES = 0.
connected if CONNECT = 1.
are unchanged, preventing output glitches.
______________________________________________________________________________________
Power-On Reset
Device Reset
USB Peripheral/Host Controller
Chip Reset
• The GPX output selector (GPXB, GPXA) is
• The bits that control the SPI interface are
• The bits that control power-down and wakeup
All other bits except the three noted in the Power-On
Reset section are cleared.
Note: The IRQ and IE bits are cleared using this reset.
This means that firmware routines that enable interrupts
should be called after a reset of this type. GPOUT7–
GPOUT0 are left unchanged during chip reset. They
are only cleared by an internal POR.
When the MAX3421E detects 21.33µs of SE0, it asserts
the URESIRQ bit, and clears certain bits. This reset is
the least inclusive of the three resets. It maintains the
bit states listed in the Power-On Reset and Chip Reset
sections, plus it leaves the following bits in their previ-
ous states:
• EPFIFO registers are unchanged.
• The GPOUT7–GPOUT0 bits are unchanged.
• The IE bit is unchanged.
• URESIE/IRQ and URESDNIE/IRQ are unchanged,
The EPFIFO registers are left in their pre-USB bus reset
states only for diagnostic purposes. Their values should
be considered invalid after a bus reset. The actual data
in the FIFOs is never cleared.
As with the chip reset, most of the interrupt request and
interrupt enable bits are cleared, meaning that the
device firmware must re-enable individual interrupts
after a bus reset. The exceptions are the interrupts
associated with the actual bus reset, allowing the SPI
master to detect the beginning and end of the host sig-
naling USB bus reset.
As a host, an SPI master instructs the MAX3421E to
generate a USB bus reset by setting the BUSRST bit in
the HCTL register (R29). The MAX3421E generates the
correctly timed signal, and asserts the BUSEVENTIRQ
bit in the HIRQ register (R25) at completion.
The MAX3421E requires a crystal with the following
specifications:
Frequency: 12MHz ±0.25%
unchanged.
unchanged: FDUPSPI, INTLEVEL, and POSINT.
behavior are unchanged: HOSCSTEN, PWRDOWN,
and SIGRWU.
allowing the SPI master to check the state of USB
bus reset.
with SPI Interface
USB Bus Reset in Peripheral Mode
USB Bus Reset in Host Mode
Crystal Selection
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