DS21Q41BT Maxim Integrated Products, DS21Q41BT Datasheet - Page 37

• Manufacturer Part Number: DS21Q41BT
• Description: IC FRAMER T1 QUAD 128-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q41BT

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TTR1/TTR2/TTR3:
TRANSMIT TRANSPARENCY REGISTERS (Address=39 to 3B Hex)
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the channel
have Bit 7 stuffing performed. However, in the D4 framing mode, bit 2 will be overwritten by a 0 when a
Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from determining
which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set to 1, then all
24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR registers are
programmed. In this manner, the TTR registers are only affecting which channels are to have robbed bit
signaling inserted into them. Please see Figure 13-9 for more details.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB)
(MSB)
(MSB)
CH16
CH24
CH16
CH24
TIDR7
CH8
CH8
SYMBOL
SYMBOL
SYMBOL
TIDR7
TIDR0
CH24
CH24
CH1
CH1
CH15
CH23
CH15
CH23
CH7
CH7
TIDR6
POSITION
POSITION
POSITION
TTR3.7
TTR1.0
TIDR.7
TIDR.0
CH14
CH22
CH14
CH22
TIR3.7
TIR1.0
CH6
CH6
TIDR5
CH13
CH21
CH13
CH21
CH5
CH5
NAME AND DESCRIPTION
Transmit Transparency Registers.
0=this DS0 channel is not transparent
1=this DS0 channel is transparent
NAME AND DESCRIPTION
Transmit Idle Registers.
0=do not insert the Idle Code into this DS0 channel
1=insert the Idle Code into this channel
NAME AND DESCRIPTION
MSB of the Idle Code
LSB of the Idle Code
TIDR4
37 of 61
CH12
CH20
CH12
CH20
CH4
CH4
TIDR3
CH11
CH19
CH11
CH19
CH3
CH3
TIDR2
CH10
CH18
CH10
CH18
CH2
CH2
TIDR1
CH17
CH17
CH1
CH9
CH1
CH9
(LSB)
(LSB)
TTR2 (3A)
TTR3 (3B)
TTR1 (29)
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
(LSB)
TIDR0
DS21Q41B