ISP1161ABD ST-Ericsson Inc, ISP1161ABD Datasheet - Page 44

• Manufacturer Part Number: ISP1161ABD
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1165; ISP1161ABD,157

Philips Semiconductors
10. HC registers
9397 750 13962
Product data
No matter which method is used to wake up the HC from USBSuspend state, the
corresponding interrupt bits must be enabled before the HC goes into USBSuspend
state so that the microprocessor can receive the correct interrupt request to wake up
the HC.
The HC contains a set of on-chip control registers. These registers can be read or
written by the Host Controller Driver (HCD). The Control and Status register sets,
Frame Counter register sets, and Root Hub register sets are grouped under the
category of HC Operational registers (32 bits). These operational registers are made
compatible to OpenHCI (Host Controller Interface) Operational registers. This allows
the OpenHCI HCD to be easily ported to ISP1161A.
Reserved bits may be defined in future releases of this specification. To ensure
interoperability, the HCD must not assume that a reserved field contains logic 0.
Furthermore, the HCD must always preserve the values of the reserved field. When a
R/W register is modified, the HCD must first read the register, modify the bits desired,
and then write the register with the reserved bits still containing the original value.
Alternatively, the HCD can maintain an in-memory copy of previously written values
that can be modified and then written to the HC register. When a ‘write to set’ or ‘clear
the register’ is performed, bits written to reserved fields must be logic 0.
As shown in
32-bit Operational registers are similar the offsets defined in the OHCI specification
with the addresses being equal to offset divided by 4.
•
•
Under the USBSuspend state, once pin H_WAKEUP goes HIGH, after 160 µs, the
internal clock will be up. If pin H_WAKEUP continues to be HIGH, then the internal
clock will be kept running, and the microprocessor can set the HC into
USBOperational state during this time.
If H_WAKEUP goes LOW for more than 1.14 ms, the internal clock stops, and the
HC goes back into USBSuspend state.
Wake-up by pin CS (software wake-up)
During the USBSuspend state, an external microprocessor issues a chip select
signal through pin CS. This method of access to ISP1161A internal registers is a
software wake-up.
Wake-up by USB devices
For a USB bus resume, a USB device attached to the root hub port issues a
resume signal to the HC through the USB bus, switching the HC from
USBSuspend state to USBResume state. This will also set the ResumeDetected
bit of the HcInterruptStatus register (03H - read, 83H - write).
Table
Rev. 03 — 23 December 2004
7, the addresses (the commands for accessing registers) of these
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ISP1161A
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