ISP1161ABD ST-Ericsson Inc, ISP1161ABD Datasheet - Page 98

• Manufacturer Part Number: ISP1161ABD
• Description: IC USB HOST/DEVICE CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1165; ISP1161ABD,157

Philips Semiconductors
Table 86:
[1]
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcDMAConfiguration register: bit allocation
CNTREN
reserved
IEP6
R/W
R/W
R/W
R/W
0
0
15
15
0
7
0
7
[1]
[1]
13.1.6 DcDMAConfiguration register (R/W: F1H/F0H)
SP_IEEOT
SHORTP
Table 85:
This command defines the DMA configuration of ISP1161A’s DC and
enables/disables DMA transfers. The command accesses the DcDMAConfiguration
register, which consists of 2 bytes. The bit allocation is given in
will clear bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1 — write/read DMA Configuration
Transaction — write/read 1 word
Bit
31 to 24
23 to 10
9
8
7
6
5
4
3
2
1
0
IEP5
R/W
R/W
R/W
R/W
0
0
14
14
0
6
0
6
[1]
[1]
EPDIX[3:0]
DcInterruptEnable register: bit description
Symbol
-
IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint.
IEP0IN
IEP0OUT
-
SP_IEEOT
IEPSOF
IESOF
IEEOT
IESUSP
IERESM
IERST
reserved
IEPSOF
IEP4
R/W
R/W
R/W
R/W
0
0
13
13
0
5
0
5
[1]
[1]
Rev. 03 — 23 December 2004
reserved
IESOF
Description
reserved; must write logic 0
Logic 1 enables interrupts from the control IN endpoint.
Logic 1 enables interrupts from the control OUT endpoint.
reserved
Logic 1 enables interrupt upon detection of a short packet.
Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF.
Logic 1 enables interrupt upon SOF detection.
Logic 1 enables interrupt upon EOT detection.
Logic 1 enables interrupt upon detection of ‘suspend’ state.
Logic 1 enables interrupt upon detection of a ‘resume’ state.
Logic 1 enables interrupt upon detection of a bus reset.
IEP3
Full-speed USB single-chip host and device controller
R/W
R/W
R/W
R/W
0
0
12
12
0
4
0
4
[1]
[1]
reserved
DMAEN
IEEOT
IEP2
R/W
R/W
R/W
R/W
0
11
11
0
3
0
3
0
[1]
reserved
reserved
IESUSP
IEP1
R/W
R/W
R/W
R/W
0
10
10
0
2
0
2
0
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
reserved
IERESM
IEP0IN
Table
ISP1161A
R/W
R/W
R/W
R/W
0
0
9
0
1
0
9
1
[1]
[1]
BURSTL[1:0]
86. A bus reset
IEP0OUT
reserved
IERST
R/W
R/W
R/W
R/W
97 of 134
0
0
8
0
0
0
8
0
[1]
[1]