CY7C63833-LFXC Cypress Semiconductor Corp, CY7C63833-LFXC Datasheet - Page 36
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CY7C63833-LFXC
Manufacturer Part Number
CY7C63833-LFXC
Description
IC USB PERIPHERAL CTRLR 32VQFN
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Datasheet
1.CY7C63833-LFXC.pdf
(83 pages)
Specifications of CY7C63833-LFXC
Controller Type
USB Peripheral Controller
Interface
USB
Voltage - Supply
4 V ~ 5.5 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
428-2258
CY7C63833-LFXC
CY7C63833-LFXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C63833-LFXC
Manufacturer:
CYPRESS
Quantity:
100
Company:
Part Number:
CY7C63833-LFXC
Manufacturer:
CYPRESS
Quantity:
1 500
Table 14-5. P0.0/CLKIN Configuration (P00CR) [0x05] [R/W]
Table 14-6. P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Document 38-08035 Rev. *K
This pin is shared between the P0.0 GPIO use and the CLKIN pin for an external clock. When the external clock input is enabled
(Bit[0] in register CPUCLKCR Table 10-3 on page 22) the settings of this register are ignored.
The use of the pin as the P0.0 GPIO is available in all the enCoRe II parts.
This pin is shared between the P0.1 GPIO use and the CLKOUT pin. When CLK output is set, the internally selected clock is
sent out onto P0.1CLKOUT pin.
The use of the pin as the P0.1 GPIO is available in all the enCoRe II parts.
Bit 7: CLK Output
0 = The clock output is disabled.
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
Pull-Up Enable
TTL Threshold
Output Enable
Open Drain
3.3V Drive
High Sink
Port Data
Data In
CLK Output
Reserved
R/W
7
--
0
7
0
Int Enable
Int Enable
R/W
R/W
6
0
6
0
Int Act Low
Int Act Low
Figure 14-1. Block Diagram of a GPIO
R/W
R/W
5
0
5
0
TTL Thresh
TTL Thresh
VREG
VREG GND
R/W
R/W
4
0
4
0
Reserved
Reserved
3
--
0
3
--
0
(Table 10-7
VREG
V
V
Open Drain
Open Drain
CC
CC
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
GND
on page 26) is driven out to the pin.
R
UP
Pull up Enable
Pull Up Enable
R/W
R/W
1
0
1
0
GPIO
V
PIN
CC
Output Enable
Output Enable
Data Out
Page 36 of 83
R/W
R/W
0
0
0
0
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