DP8409AN National Semiconductor, DP8409AN Datasheet - Page 5

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

Conditions for All Modes
When the DP8409A is in a refresh mode the RF I O pin
indicates that the on-chip refresh counter has reached its
end-of-count This end-of-count is selectable as 127 255 or
512 to accommodate 16k 64k or 256k DRAMs Although
the end-of-count may be chosen to be any of these the
counter always counts to 511 before rolling over to zero
READ WRITE AND READ-MODIFY-WRITE CYCLES
The output signal WE determines what type of memory
access cycle the memory will perform If WE is kept high
while CAS goes low a read cycle occurs If WE goes low
before CAS goes low a write cycle occurs and data at DI
(DRAM input data) is written into the DRAM as CAS goes
low If WE goes low later than t
a read occurs and DO (DRAM output data) becomes valid
then data DI is written into the same address in the DRAM
when WE goes low In this read-modify-write case DI and
DO cannot be linked together The type of cycle is therefore
controlled by WE which follows WIN
POWER-UP INITIALIZE
When V
clears the refresh counter the internal control flip-flops and
set the End-of-Count of the refresh counter to 127 (which
may be changed via Mode 7) As V
2 3V it holds the output control signals at a level of one
Schottky diode-drop below V
TRI-STATE As V
outputs is granted to the system
CC
is first applied to the DP8409A an initialize pulse
CC
increases above 2 3V control of these
CC
CWD
and the output address to
after CAS goes low first
FIGURE 2 External Control Refresh Cycle (Mode 0)
CC
increases to about
(Continued)
5
Figure 2 is the Externally Controlled Refresh Timing In this
DP8409A Functional Mode
Descriptions
Note All delay parameters stated in text refer to the DP8409A Substitute
MODE 0 EXTERNALLY CONTROLLED REFRESH
mode the input address latches are disabled from the ad-
dress outputs and the refresh counter is enabled When
RAS occurs the enabled row in the DRAM is refreshed In
the Externally Controlled Refresh mode all RAS outputs are
enabled following RASIN and CAS is inhibited This refresh-
es the same row in all four banks The refresh counter incre-
ments when either RASIN or RFSH goes low-to-high after a
refresh RF I O goes low when the count is 127 255 or
511 as set by End-of-Count (see Table III) with RASIN and
RFSH low To reset the counter to all zeros RF I O is set
low through an external open-collector driver
During refresh RASIN and RFSH must be skewed tran-
sitioning low such that the refresh address is valid on the
address outputs of the controller before the RAS outputs go
low The amount of time that RFSH should go low before
RASIN does depends on the capacitive loading of the ad-
dress and RAS lines For the load specified in the switching
characteristics of this data sheet 10 ns is sufficient Refer
to Figure 2
To perform externally controlled burst refresh RASIN is tog-
gled while RFSH is held low The refresh counter incre-
ments with RASIN going low to high so that the DRAM rows
are refreshed in succession by RASIN going high to low
the respective delay numbers for the DP8409-2 or DP8409-3 when
using these devices
TL F 8409 – 9