DP8409AN National Semiconductor, DP8409AN Datasheet - Page 8

• Manufacturer Part Number: DP8409AN
• Description: IC CONTROLLER DYNAMIC RAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8409AN

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN

DP8409A Functional Mode Descriptions
dress input latch is enabled onto the address bus About
14 ns after the column address is valid CAS goes low (t
When RAS and CAS go high the refresh counter increments
to the next row and the cycle repeats Since WE is kept low
in this mode the data at DI (input data) of the DRAMs is
written into each row of the latched column During each
cycle RAS is high for two periods of RGCK and low for two
periods giving a total write-cycle time of 400 ns minimum
which is adequate for most 16k and 64k DRAMs On the last
row of a column RF I O increments the external counter to
the next column address
e a
14 ns) strobing the column address into the DRAMs
FIGURE 5a DP8409A Extra Circuitry Required for All-RAS Auto Write Mode Mode 3a
FIGURE 5b DP8409A All-RAS Auto Write Mode Mode 3a Timing Waveform
ASC
8
(Continued)
At the end of the last column address an interrupt is gener-
ated from the external counter to let the system know that
initialization has been completed During the entire initializa-
tion time the system can be performing other initialization
functions This approach to memory initialization is both au-
tomatic and fast For instance if four banks of 64k DRAMs
are used and RGCK is 100 ns a write cycle to the same
location in all four banks takes 400 ns so the total time
taken in initializing the 64k DRAMs is 65k
26 ms When the system receives the interrupt the external
counter must be permanently disabled ADS and CS are
interfaced by the system and the DP8409A mode is
changed The interrupt must then be disabled
TL F 8409 – 12
c
TL F 8409– 13
400 ns or