DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 26

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

5 0 Buffer Management
5 3 DESCRIPTOR DATA ALIGNMENT
All fields used by descriptors (RXpkt xxx RXrsrc xxx and
TXpkt xxx) are word quantities (16-bit) and must be aligned
to word boundaries (A0
word boundaries (A1 A0
ceive Buffer Area (RBA) must also be aligned to a word
boundary in 16-bit mode and a long word boundary in 32-bit
mode The fragments in the Transmit Buffer Area (TBA)
however may be aligned on any arbitrary byte boundary
5 4 RECEIVE BUFFER MANAGEMENT
The Receive Buffer Management operates on three areas in
memory into which data status and control information are
written during reception (Figure 5-3) These three areas
must be initialized (Section 5 4 4) before enabling the re-
ceiver (setting the RXEN bit in the Command Register) The
Receive Resource Area (RRA) contains descriptors that lo-
cate Receive Buffer Areas in system memory These de-
scriptors are denoted by R1 R2 etc in Figure 5-3 Packets
(denoted by P1 P2 etc ) can then be buffered into the cor-
responding RBAs Depending on the size of each buffer
area and the size of the packet(s) multiple or single packets
are buffered into each RBA The Receive Descriptor Area
(RDA) contains status and control information for each
packet (D1 D2 etc in Figure 5-3 ) corresponding to each
received packet (D1 goes with P1 D2 with P2 etc )
When a packet arrives the address recognition logic checks
the address for a Physical Multicast or Broadcast match
and if the packet is accepted the SONIC-T buffers the
packet contiguously into the selected Receive Buffer Area
(RBA) Because of the previous end-of-packet processing
the SONIC-T assures that the complete packet is written
into a single contiguous block When the packet ends the
SONIC-T writes the receive status byte count and location
of the packet into the Receive Descriptor Area (RDA) The
SONIC-T then updates its pointers to locate the next avail-
able descriptor and checks the remaining words available in
the RBA If sufficient space remains the SONIC-T buffers
the next packet immediately after the previous packet If the
current buffer is out of space the SONIC-T fetches a Re-
source Descriptor from the Receive Resource Area (RRA)
acquiring an additional buffer that has been previously allo-
cated by the system
e
e
0) for 16-bit memory and to long
0 0) for 32-bit memory The Re-
FIGURE 5-3 Overview of Receive Buffer Management
(Continued)
26
5 4 1 Receive Resource Area (RRA)
As buffer memory is consumed by the SONIC-T for storing
data the Receive Resource Area (RRA) provides a mecha-
nism that allows the system to allocate additional buffer
space for the SONIC-T The system loads this area with
Resource Descriptors that the SONIC-T in turn reads as its
current buffer space is used up Each Resource Descriptor
consists of a 32-bit buffer pointer locating the starting point
of the RBA and a 32-bit word count that indicates the size of
the buffer in words (2 bytes per word) The buffer pointer
and word count are contiguously located using the format
shown in Figure 5-4 with each component composed of
16-bit fields The SONIC-T stores this information internally
and concatenates the corresponding fields to create 32-bit
long words for the buffer pointer and word count Note that
in 32-bit mode the upper word (D
the SONIC-T This area may be used for other purposes
since the SONIC-T never writes into the RRA
The SONIC-T organizes the RRA as a circular queue for
efficient processing of descriptors Four registers define the
RRA The first two the Resource Start Area (RSA) and the
Resource End Area (REA) registers determine the starting
and ending locations of the RRA and the other two regis-
ters update the RRA The system adds descriptors at the
address specified by the Resource Write Pointer (RWP)
and the SONIC-T reads the next descriptor designated by
the Resource Read Pointer (RRP) The RRP is advanced 4
words in 16-bit mode (4 long words in 32-bit mode) after the
SONIC-T finishes reading the RRA and automatically wraps
around to the beginning of the RRA once the end has been
reached When a descriptor in the RRA is read the
RXrsc buff pt0 1 is loaded into the CRBA0 1 registers and
the RXrsc buff wc0 1 is loaded into the RBWC0 1 regis-
ters
The alignment of the RRA is confined to either word or long
word boundaries depending upon the data width mode In
16-bit mode the RRA must be aligned to a word boundary
(A0 is always zero) and in 32-bit mode the RRA is aligned
to a long word boundary (A0 and A1 are always zero)
TL F 11719 – 16
k
31 16
l
) is not used by