DP83934AVQB National Semiconductor, DP83934AVQB Datasheet - Page 67

• Manufacturer Part Number: DP83934AVQB
• Description: IC CTRLR ORIENT NETWORK 160PLCC
• Manufacturer: National Semiconductor

Specifications of DP83934AVQB

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83934AVQB

7 0 Bus Interface
7 3 6 Bus Exceptions (Bus Retry)
The SONIC-T provides the capability of handling errors dur-
ing the execution of the bus cycle (Figure 7-18)
The system asserts BRT (bus retry) to force the SONIC-T to
repeat the current memory cycle When the SONIC-T de-
tects the assertion of BRT it completes the memory cycle
at the end of T2 and gets off the bus by deasserting BGACK
or HOLD Then if Latched Bus Retry mode is not set (LBR
in the Data Configuration Register Section 6 3 2) the
SONIC-T requests the bus again to retry the same memory
cycle If Latched Bus Retry is set though the SONIC-T will
not retry until the BR bit in the ISR (see Section 6 3 6) has
been reset and BRT is deasserted BRT has precedence of
terminating a memory cycle over DSACK0 1 STERM or
RDYi
BRT may be sampled synchronously or asynchronously by
setting the EXBUS bit in the DCR (see Section 6 3 2) If
synchronous Bus Retry is set BRT is sampled on the rising
edge of T2 If asynchronous Bus Retry is set BRT is double
synchronized from the falling edge of T1 The asynchronous
setup time does not need to be met but doing so will guar-
antee that the bus exception will occur in the current bus
cycle instead of the next bus cycle Asynchronous Bus Re-
try may only be used when the SONIC-T is set to asynchro-
nous mode
Note 1 The deassertion edge of HOLD is dependent on the PH bit in the
Note 2 If Latched Bus retry is set BRT need only satisfy its setup time (the
Note 3 If DSACK0 1 STERM or RDYi remain asserted after BRT the next
7 3 7 Slave Mode Bus Cycle
The SONIC-T’s internal registers can be accessed by one of
two methods (BMODE
ods the SONIC-T is a slave on the bus This section de-
scribes the SONIC-T’s slave mode bus operations
7 3 7 1 Slave Cycle for BMODE
The system accesses the SONIC-T by driving SAS CS
SRW and RA
bus cycle but the SONIC-T will not actually start a slave
cycle until CS has also been asserted CS should not be
asserted before SAS is driven low as this will cause improp-
DCR2 (see Section 6 3 7) Also BGACK is driven high for about 0 5
bus clocks before going TRI-STATE
hold time is not important) Otherwise BRT must remain asserted
until after the Th state
memory cycle may be adversely affected
k
5 0
l
These signals will be sampled each
e
1 or BMODE
(Continued)
e
1
e
FIGURE 7-18 Bus Exception (Bus Retry)
0) In both meth-
67
er slave operation Once SAS has been driven low between
one and two bus clocks after the assertion of CS SMACK
will be asserted to signify that the SONIC-T has started the
slave cycle Although CS is an asynchronous input meeting
its setup time (as shown in Figures 7-19 and 7-20 ) will guar-
antee that SMACK which is asserted off of a falling edge
will be asserted 1 bus clock after the falling edge that CS is
clocked in on This is assuming that the SONIC-T is not a
bus master when CS was asserted If the SONIC-T is a bus
master then when CS is asserted the SONIC-T will com-
plete its current master bus cycle and get off the bus tempo-
rarily (see Section 7 4 8) In this case SMACK will be as-
serted 5 bus clocks after the falling edge that CS was
clocked in on This is assuming that there were no wait
states in the current master mode access Wait states will
increase the time for SMACK to go low by the number of
wait states in the cycle
If the slave access is a read cycle (Figure 7-19) then the
data will be driven off the same edge as SMACK If it is a
write cycle (Figure 7-20) then the data will be latched in
exactly 2 bus clocks after the assertion of SMACK In either
case DSACK0 1 are driven low 2 bus clocks after SMACK
to terminate the slave cycle For a read cycle the assertion
of DSACK0 1 indicates valid register data and for a write
cycle the assertion indicates that the SONIC-T has latched
the data The SONIC-T deasserts DSACK0 1 SMACK and
the data if the cycle is a read cycle at the rising edge of SAS
or CS depending on which is deasserted first
Note 1 Although the SONIC-T responds as a 32-bit peripheral when it
Note 2 For multiple register accesses CS can be held low and SAS can be
Note 3 If memory request (MREQ) follows a chip select (CS) it must be
Note 4 When CS is deasserted it must remain deasserted for at least one
Note 5 The way in which SMACK is asserted due to CS is not the same as
drives DSACK0 1 low it transfers data only on lines D
used to delimit the slave cycle (this is the only case where CS may
be asserted before SAS) In this case SMACK will be driven low
due to SAS going low since CS has already been asserted Notice
that this means SMACK will not stay asserted low during the entire
time CS is low (as is the case for MREQ Section 7 3 8)
asserted at least 2 bus clocks after CS is deasserted Both CS and
MREQ must not be asserted concurrently
bus clock
the way in which SMACK is asserted due to MREQ The assertion
of SMACK is dependent upon both CS and SAS being low not just
CS This is not the same as the case for MREQ (see Section 7 3 8)
The assertion of SMACK in these two cases should not be con-
fused
TL F 11719 – 45
k
15 0
l