DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 21

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

5.0 DP83850C Applications
5.1 MII Interface Connections
The DP83850C's interface to DP83840A PHY devices is
fully described in the Application Note – AN1069
"100BASE-TX Unmanaged Repeater Design Recommen-
dations". Designers should be aware that there are signifi-
cant
layout of this interface and they should consult this Applica-
5.2 Repeater ID Interface
The repeater ID interface is shown in Figure 6. It consists
of a bank of DIP switches or links to set the RID number for
the DP83850C to use as its IR_VECT[4:0] number.
5.3 Inter Repeater Bus Connections
For a simple stand-alone repeater that cannot be stacked,
no inter repeater bus transceivers/drivers are required and
the inter repeater bus interface is simple. An example of
this is shown in Figure 7.
DP83840A
DP83840A
DP83840A
issues involved in the signal timing, loading and
100PHY
100PHY
100PHY
#11
#0
#1
RX_CLK
RXD2
RXD3
RX_ER
RX_ER
RXD0
RXD1
RX_DV
RX_CLK
RXD0
RXD1
RXD3
RXD2
RX_DV
RX_CLK
RXD3
RXD0
RXD2
RX_ER
RXD1
RX_DV
Figure 5. Recommended DP83840A to DP83850C Connections
'ABT541
'ABT541
'ABT541
T
T
21
tion Note and/or their National Semiconductor representa-
tive prior to attempting a design. Further system timing
analysis shows that the RXD[3:0], RX_DV and RX_ER sig-
nals should be latched into the DP83850C from the con-
nected DP83840s. Figure 5 shows the recommended
scheme. This ensures system timing can be met for hub
stacks.
For a stackable hub design, the DP83850C's Inter
Repeater Bus connections are complex and have many
issues regarding signal timing, loading and layout.
example design for a TTL level inter repeater bus is given
in Figure 8. It should be noted that this is a single example
of possible connections to an inter repeater bus. There are
many other possible ways to design this interface. Design-
ers should be aware that timing, particularly skew between
clock and data, is critical. For this reason, the use of LS, S,
TTL, or CMOS logic drivers is not recommended. The ABT
family of logic is recommended, as well as the FAST® fam-
ily could possibly be made to work too. Also recommended
P = Pull -Downs, 1.2k ohms
T = AC Termination - see AN-1069
P
T
T
T
T
T
T
T
D
'ABT174
'F04
/MR
Q
P
P
P
P
P
P
RX_CLK
RXD1
RXD2
RXD3
RX_DV
RX_ER
RXD0
RXE0
RXE11
DP83850C
100RIC
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