DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 6
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DP83850CVF
Manufacturer Part Number
DP83850CVF
Description
IC CONTROLLER INTERFACE 132-PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83850CVF.pdf
(37 pages)
Specifications of DP83850CVF
Controller Type
Ethernet Repeater Interface Controller
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
295mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83850CVF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83850CVF
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83850CVF
Manufacturer:
NS/国半
Quantity:
20 000
2.0 Pin Descriptions
2.1 Physical Layer Interface
RXD[3:0]
RXE[11:0]
RX_DV
RX_ER
RXC
CRS[11:0]
TXE[11:0]
TX_RDY
TX_ER
TXD[3:0]
Note: A table showing pin type designation is given in section 2.5
Signal Name Type
I
O, L high (low) Receive Enable: Asserted to the respective Physical Layer chip to enable its Receive
I
I
I
I
O, L
O, L
O, M
O, H
Active
high
high
high
high
high
high
high
—
—
Receive Data: Nibble data inputs from each Physical layer chip. Up to 12 ports are sup-
ported.
Note: Input buffer has a weak pull-up.
Data. These pins are either active high or active low depending on the polarity of RSM3
pin as shown below:
RXE[11:0]
Active High
Active Low
Receive Data Valid: Asserted High when valid data is present on RXD[3:0].
Note: To ensure that during idle, when 100PHYs TRI-STATE®, this signal is NOT inter-
preted as “logic one” by the repeater, a 1k pull down resistor must be placed on this
pin. The location on this pull down should be between the repeater and the nearest tri-
stateable component to the repeater.
Receive Error: The physical Layer asserts this signal high when it detects receive error.
When this signal is asserted, the 100PHY (TX or T4) device indicates the type of error
on RXD[3:0] as shown below. Note that this data is passed only to the Inter Repeater
Bus, and not onto the TX Bus:
RX_ER
1
code will never be generated.
2
the DP83850C only enables a 100PHY when its CRS is asserted, these error codes will
never be passed through the chip.
Note: Input buffer has a weak pull-down.
Receive Clock: Recovered clock from the Physical Layer device. RXD, RX_DV, and
RX_ER are generated from the falling edge of this clock.
Note: Input buffer has a weak pull-down.
Carrier Sense: Asynchronous carrier indication from the Physical Layer device.
Transmit Enable: Enables corresponding port for transmitting data.
Transmit Ready: Indicates when a transmit is in progress. Essentially, this signal is the
logical 'OR' of all TXEs.
Transmit Error: Asserted high when a code violation is requested to be transmitted.
Transmit Data: Nibble data output to be transmitted by each Physical Layer device.
These error codes will only appear when CRS from the 100PHY is not asserted. Since
The 100PHY must be configured with the Elasticity Buffer bypassed; hence this error
0
1
1
1
1
1
RSM3
Unconnected or pulled high
Pulled down
RXD[3:0]
data
1h
3h
4h
0h
2h
1
2
2
6
Receive Error Condition
Normal data reception
Symbol code violation
Elasticity Buffer Over/Under-run
Invalid Frame Termination
Reserved
10Mb Link Detected
Description
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