DP83936AVUL-25 National Semiconductor, DP83936AVUL-25 Datasheet - Page 48
![IC CTRLR ORIENT NETWORK 160PQFP](/photos/6/83/68312/14-160-pqfp_sml.jpg)
DP83936AVUL-25
Manufacturer Part Number
DP83936AVUL-25
Description
IC CTRLR ORIENT NETWORK 160PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83936AVUL-20.pdf
(104 pages)
Specifications of DP83936AVUL-25
Controller Type
Network Interface Controller (NIC)
Interface
Twisted Pair
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
140mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83936AVUL-25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83936AVUL-25
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83936AVUL-25
Manufacturer:
NS/国半
Quantity:
20 000
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6 0 SONIC-T Registers
6 4 5 Interrupt Mask Register (Continued)
Bit
7
6
5
4
3
2
1
0
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TCEN GENERAL PURPOSE TIMER COMPLETE enable
0 disable
1 enables interrupts when the general purpose timer has rolled over from 0000 0000h to FFFF FFFFh
RDEEN RECEIVE DESCRIPTORS EXHAUSTED enable
0 disable
1 enables interrupts when all receive descriptors in the RDA have been exhausted
RBEEN RECEIVE BUFFERS EXHAUSTED enable
0 disable
1 enables interrupts when all resource descriptors in the RRA have been exhausted
RBAEEN RECEIVE BUFFER AREA EXCEEDED enable
0 disable
1 enables interrupts when the SONIC-T attempts to buffer data beyond the end of the Receive Buffer Area
CRCEN CRC TALLY COUNTER WARNING enable
0 disable
1 enables interrupts when the CRC tally counter has rolled over from FFFFh to 0000h
FAEEN FRAME ALIGNMENT ERROR (FAE) TALLY COUNTER WARNING enable
0 disable
1 enables interrupts when the FAE tally counter rolled over from FFFFh to 0000h
MPEN MISSED PACKET (MP) TALLY COUNTER WARNING enable
0 disable
1 enables interrupts when the MP tally counter has rolled over from FFFFh to 0000h
RFOEN RECEIVE FIFO OVERRUN enable
0 disable
1 enables interrupts when the receive FIFO has overrun
(Continued)
48
Description