DP83936AVUL-25 National Semiconductor, DP83936AVUL-25 Datasheet - Page 95
![IC CTRLR ORIENT NETWORK 160PQFP](/photos/6/83/68312/14-160-pqfp_sml.jpg)
DP83936AVUL-25
Manufacturer Part Number
DP83936AVUL-25
Description
IC CTRLR ORIENT NETWORK 160PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83936AVUL-20.pdf
(104 pages)
Specifications of DP83936AVUL-25
Controller Type
Network Interface Controller (NIC)
Interface
Twisted Pair
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
140mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
160-MQFP, 160-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83936AVUL-25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DP83936AVUL-25
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DP83936AVUL-25
Manufacturer:
NS/国半
Quantity:
20 000
T56
T60
T63
T64
T67
T69
T69a
T74
T75a
T77
T77a
T77b
T78
T79a
T81
T82
T85a
T86
Number
9 0 AC and DC Specifications
Note 1 This figure shows a slave access to the SONIC-T when the SONIC-T is idle or rather not in master mode If the SONIC-T is a bus master there will be
some differences as noted in the Memory Arbitration Slave Access diagram The BSCK states (T1 T2 etc ) are the equivalent processor states during a slave
access
Note 2 bcyc
Note 3 It is not necessary to meet the setup time for CS and SAS (T56 and T69) since these signals are asynchronously sampled Meeting the setup time for these
signals however makes it possible to use T60 to determine when SMACK will be asserted SAS may be asserted anytime before the next falling edge of the clock
that the CS is sampled on (as shown by specification T69) For multiple register accesses CS can be held low and SAS can be used to delimit the slave cycle
(T69a must be met in order to terminate and start another cycle) In this case SMACK will be asserted as soon as T69 timing is met
Note 4 T60 could range from 1 bus clock minimum to 5 bus clock maximum depending on what state machine the SONIC-T is in when the CS signal is asserted
This timing is not tested but is guaranteed by design This specification assumes that both T56 is met for CS and T69 is met for SAS T60 specification also
assumes that there were no wait states in the current master mode access (if CS is asserted when SONIC-T is in Master Mode) If there were wait states then it
would increase to T60 futher
Note 5 It is not necessary to meet the setup time for SAS (T69a) since this signal is asynchronously sampled Meeting the setup time for this signal however will
ensure DSACK0 1 becomes TRI-STATE (T77b) and SMACK goes high (T79) at the falling edge of T1 Both CS and SAS could cause DSACK0 1 to deassert but
only SAS could cause DSACK0 1 to become TRI-STATE
Note 6 The timing value includes an RC delay inherent in the test measurement These signals typically TRI-STATE 7 ns earlier enabling other devices to drive
these lines without contention
e
CS Asynchronous Setup to BSCK (Notes 3 4)
CS Valid to SMACK Low (Notes 2 3 4)
Register Address Setup to SAS
Register Address Hold from SAS
SRW (Read) Setup to SAS
SAS Asynchronous Setup to BSCK (Notes 3 4)
SAS Asynchronous Setup to BSCK (Notes 3 5)
SRW (Read) Hold from SAS
BSCK to DSACK0 1 Low
CS to DSACK0 1 High (Note 5)
SAS to DSACK0 1 High (Note 5)
BSCK to DSACK0 1 TRI-STATE (Note 5)
Skew between DSACK0 1
BSCK to SMACK High (Note 5)
BSCK to SMACK Low
BSCK to Register Data Valid
Minimum CS Deassert Time (Notes 2 3)
SAS to Register Data TRI-STATE (Note 6)
bus clock cycle time (T3)
Parameter
(Continued)
95
Min
8
1
6
8
4
7
5
8
1
20 MHz
Max
20
20
31
19
19
22
44
42
5
3
Min
7
1
5
7
3
6
4
7
1
25 MHz
Max
18
18
29
17
17
20
42
40
5
3
Min
6
1
4
6
2
5
3
6
1
33 MHz
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Max
16
16
27
15
15
18
40
38
2
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Units
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