MC33389CDW Freescale Semiconductor, MC33389CDW Datasheet - Page 24
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MC33389CDW
Manufacturer Part Number
MC33389CDW
Description
IC SYSTEM BASE W/CAN 28-SOIC
Manufacturer
Freescale Semiconductor
Datasheet
1.MC33389DDWR2.pdf
(49 pages)
Specifications of MC33389CDW
Controller Type
System Basis Chip
Interface
CAN
Voltage - Supply
5.5 V ~ 18 V
Current - Supply
45mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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received before the software timing configuration (SWCR
register), it will not be taken into account by the SBC (except
for the go-to Emergency mode).
Correspondence Between SBC and CAN Transceiver
Modes
modes versus SBC modes.
Table 14. CAN Modes vs. SBC Modes
Watchdog
microcontroller operation in the Normal and Stand-by modes.
24
33389
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
When SBC Is In The Following
Normal and V2 OFF (over load)
In case V2 is turned OFF either
short to ground or V2 over tem-
TXRX or RX Only mode after a
mode) or by the SBC itself due
perature) the CAN is automati-
cally set into the Bus Stand-by
ECU
connected
to battery
when V2 is back to 5.0 V. The
CAN must be re configured to
to V2 over load condition (V2
mode and does not return to
Note: In the Normal Request mode, if a SPI command is
Table 14
The software window watchdog function monitors the
by SPI command (Stand-by
TXRX mode automatically
Normal Request
Reset Condition
Figure 8. Typical Behavior at Power-On
V2 turn OFF
Emergency
Stand-by
Normal
V1 low
provides different possible CAN transceiver
Mode
Sleep
Reset
V1 on
( reset
released )
Request
Normal
timing configuration
No SPI SW
at t=75ms
SPI SW
timing configuration
at t<75ms
RXTX or RXOnly or BusStand-by
Bus Stand-by Mode
Bus Stand-by Mode
SPI go to Emergency
at t<75ms
CAN Transceiver
Bus Stand-by
Bus Stand-by
Bus Stand-by
Bus Stand-by
Can Be In
Emergency
Normal
Sleep
The window watchdog timing is derived from the SBC clock.
The desired watchdog timing must be first transmitted during
the SBC configuration, in the Normal Request mode, via SPI
to SWCR. It can also be changed later on. Selectable
watchdog timings are 5.0 ms, 10 ms, 20 ms, 33 ms, 50 ms,
75 ms, 100 ms and 200 ms. These timings correspond to the
full disable window plus full enable window.
Window, the internal counter is reset and begins a new
disable window. The SBC triggers the watchdog word at CS
low-to-high transition. Any watchdog trigger outside the
Enable Window leads to an SBC reset.
• Normal and Stand-by Modes— The SBC get the watchdog
• Normal Request, Sleep, and Emergency Mode—
WAKE-UP CAPABILITIES
Forced Wake-Up
V3 register. It is used to automatically wake-up the system by
supplying V1 with proper reset in the Sleep mode. This
corresponds to jump into the Normal Request mode. If the
SBC is not properly configured within 75 ms, it switches back
to the Sleep mode until the next wake-up. If both Cyclic
Sense and Forced Wake-Up are enabled by the SPI while in
the Sleep mode, only Cyclic Sense is active.
256 ms, 512 ms, 1024 ms, 2048 ms, and 8192 ms chosen by
SPI in the Cyclic Timing Control Register (CYTCR).
Wake-Up Inputs (Local Wake-Up)/Cyclic Sense
events such as closing/opening of switches. The wake-up
feature is available in Normal, Stand-by, and Sleep modes.
Watchdog Trigger
SBC Watchdog Window
SBC-Reset OUT
As soon as the watchdog trigger is received in the Enable
word from the microcontroller via SPI in the Normal mode.
In case of a trigger time failure (no trigger or trigger outside
the Enable Window) the SBC reset is switched to active.
Watchdog is not active in these modes.
Several wake-up capabilities are available.
The forced wake-up is enabled and disabled by SPI in the
The period of Forced Wake-Up are 32 ms, 64 ms, 128 ms,
SBC provides three wake-up inputs to monitor external
50%
Disabled Window
Figure 9. Window Watchdog Timing
Nom. Trigger Period
Analog Integrated Circuit Device Data
Watchdog Timing
Earliest Trigger Time
Freescale Semiconductor
Enable Window
50%
Time Out
Trigger
Latest
Latest
Reset
Time
Time