SAB82525H-V21 Infineon Technologies, SAB82525H-V21 Datasheet - Page 11

• Manufacturer Part Number: SAB82525H-V21
• Description: IC CONTROLLER SERIAL 44-MQFP
• Manufacturer: Infineon Technologies

Specifications of SAB82525H-V21

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAB82525H-V21; SAB82525H-V21IN

Pin No.
P-LCC P-MQFP
Pin Definitions and Functions (cont’d)
16
10
15
11
14
12
13
17
Semiconductor Group
9
14
21
15
20
16
19
17
18
22
Symbol
RXDA
RXDB
RTSA
RTSB
CTSA/
CXDA
CTSB/
CXDB
TXDA
TXDB
RES
Input (I)
Output (O)
I
O
I
O
I
Function
Receive Data (channel A/channel B)
Serial data is received on these pins at standard TTL or
CMOS levels.
Request to Send (channel A/channel B)
When the RTS bit in the mode register is set, the RTS
signal goes low. When the RTS is reset, the signal goes
high if the transmitter has finished and there is no further
request for a transmission.
In a bus configuration, this pin can be programmed via
CCR2 to:
–
–
–
Clear to Send (channel A/channel B)
A low on the CTS inputs enables the respective transmitter.
Additionally, an interrupt may be issued if a state transition
occurs at the CTS pin (programmable feature). If no "Clear
To Send" function is required, the CTS inputs can be
connected directly to V
Collision Data (channel A/channel B)
In a bus configuration, the external serial bus must be
connected to the respective C D pin for collision
detection.
Transmit Data (channel A/channel B)
Transmit data is shifted out via these pins at standard TTL
or CMOS levels. These pins can be programmed to work
either as push-pull, or open drain outputs supporting bus
configurations.
RESET
A high signal on this input forces the HSCX into the reset
state. The HSCX is in power-up mode during reset and in
power-down mode after reset. The minimum pulse width is
1.8 s.
go low during the actual transmission of a frame shifted
by one clock period, excluding collision bits
go low during the reception of a data frame
stay always high (RTS disabled).
11
SS
.
SAB
SAB
SAF
SAF
82525
82526
82525
82526