ADM8513X-AD-T-1 Infineon Technologies, ADM8513X-AD-T-1 Datasheet - Page 29

• Manufacturer Part Number: ADM8513X-AD-T-1
• Description: IC CTRLR USB TO EHTERNET 48-LQFP
• Manufacturer: Infineon Technologies

Specifications of ADM8513X-AD-T-1

• Controller Type: Ethernet Controller (LAN)
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 150mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADM8513XADT1X; ADM8513XADT1XP; SP000077769

Table 64
Register Short Name
WUF2M_15
WUF2O
WUF2CRCL
WUF2CRCH
Res23
Res24
Res25
Res26
Res27
WUC
Res28
WUS
IPHYC
GPIO54C
Res29
GPIO10C
GPIO32C
Test
TM
The register is addressed wordwise.
Table 65
Mode
read/write
read
Read only
Read virtual
Latch high,
self clearing
Latch low,
self clearing
Latch high,
mask clearing
Latch low,
mask clearing
Data Sheet
Registers Overview (cont’d)
Register Access Types
Symbol Description HW
rw
r
ro
rv
lhsc
llsc
lhmk
llmk
Register Long Name
Wakeup Frame 2 Mask 15
Wakeup Frame 2 Offset
Wakeup Frame 2 CRC Low
Wakeup Frame 2 CRC High
Reserved 23
Reserved 24
Reserved 25
Reserved 26
Reserved 27
Wakeup Control
Reserved 28
Wakeup Status
Internal PHY Control
GPIO[5:4] Control
Reserved 29
GPIO[1:0] Control
GPIO[3:2] Control
TEST
Test Mode
Register is used as input for the HW
Register is written by HW (register
between input and output -> one cycle
delay)
Register is set by HW (register between
input and output -> one cycle delay)
Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
Latch high signal at high level, clear on
read
Latch high signal at low-level, clear on
read
Latch high signal at high level, register
cleared with written mask
Latch high signal at low-level, register
cleared on read
29
Description SW
Register is readable and writable by SW
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
SW can only read this register
SW can only read this register
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared (1 clears)
SW can read the register, with write mask
the register can be cleared (1 clears)
Offset Address
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Registers Description
Rev. 1.21, 2005-12-05
Page Number
56
56
58
58
33
33
33
34
34
59
34
60
60
61
34
62
63
64
64
Data Sheet
ADM8513